Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-03-22
2011-03-22
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S112000
Reexamination Certificate
active
07913206
ABSTRACT:
An improved method and mechanism for data partitioning for a DRC tool is disclosed that efficiently and effectively allows parallelization and multithreading to occur for DRC analysis of the IC design. Data partitioning is performed to allow some of the data to be processed in parallel by distributed processing units, while allowing other of the data to be processed in parallel by multiple threads. This can be accomplished by identifying different types of rules and data, and having different types of processing for the different types of rules and data. Certain types of rules/data will be processed with multi-threaded processing and other types of rules/data will be processed in parallel using distributed processing units.
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Sandoval Patrick
Siek Vuthe
Vista IP Law Group LLP
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