Parallel intrusion search in hierarchical VLSI designs with...

Details Parallel intrusion search in hierarchical VLSI designs with... Parallel intrusion search in hierarchical VLSI designs with...

2011-08-23

2011-08-23

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S125000

Reexamination Certificate

active

08006207

ABSTRACT:
Mechanisms are provided for performing intrusion searching of a hierarchical integrated circuit design. These mechanisms may receive the hierarchical integrated circuit design and perform a parallel intrusion search operation, that utilizes a substituting scan line, on the hierarchical integrated circuit design to identify intrusions of geometric objects in the hierarchical integrated circuit design. The mechanisms may further record intrusions of geometric objects in the hierarchical integrated circuit design identified by the parallel intrusion search operation. The parallel intrusion search operation may utilize a plurality of separate intrusion searches executed by the data processing system in parallel on the hierarchical integrated circuit design.

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R. Nair, “Scanline Approach to Fast Extraction and Checking of Layouts Described Hierarchically”, IBM Corporation, TDB n4b, Sep. 1992, pp. 163-164.

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