Semiconductor integrated circuit having improved power...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

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C257SE23142

Reexamination Certificate

active

07932610

ABSTRACT:
In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply wire to the lower cell power-supply wire. The supplementary power-supply wire and the lower cell power-supply wire are connected by two vias. The supplementary power-supply wire and the upper power-supply wire are connected by a single via. Current from the supplementary power-supply wire is divided by the two vias and then supplied to the lower cell power-supply wire. Therefore, when power is supplied from the upper power-supply wire to the lower cell power-supply wire, current concentration at the connection points of the lower cell power-supply wire to the vias is decreased, thereby reducing wire breaks caused by EM (electro migration).

REFERENCES:
patent: 5365091 (1994-11-01), Yamagishi
patent: 6031293 (2000-02-01), Hsuan et al.
patent: 6166442 (2000-12-01), Nakamura
patent: 08-046049 (1996-02-01), None
patent: 10-056162 (1998-02-01), None
patent: 11-045979 (1999-02-01), None

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