Self-aligned CMOS for bulk silicon and insulating substrate devi

Details Self-aligned CMOS for bulk silicon and insulating substrate devi Self-aligned CMOS for bulk silicon and insulating substrate devi

1976-06-17

1977-09-13

Tupman, W.

Metal working

Method of mechanical manufacture

Assembling or joining

B01J 1700

Patent

active

040472850

ABSTRACT:
The method for fabrication of a self-aligned gate CMOS structure which employs no additional masking steps as compared to the standard CMOS fabrication process, this improved process providing the advantages of self-alignment between the N+ and P+ source and drain diffusions with respect to their gate regions, and metal contact openings which do not overlap the edges of the P+ or N+ source and drain regions. The self-aligning gate region is defined by a silicon nitride gate layer. Several embodiments of the novel process are described.

REFERENCES:
patent: 3660735 (1972-05-01), McDougal
patent: 3752711 (1973-08-01), Kooi
patent: 3861968 (1975-01-01), Magdo
patent: 3921283 (1975-11-01), Shappir

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