Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2011-02-08
2011-02-08
Potter, Roy K (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S692000, C257S774000, C257SE23023
Reexamination Certificate
active
07884463
ABSTRACT:
On a semiconductor element loading face, wiring patterns are drawn out from those formed in the vicinity of the edge of the semiconductor element of the loading pads formed to correspond to the electrode terminals of the semiconductor element, and connected to via pads formed in the vicinity of the edge of the semiconductor element loading face; area pads constructed of the loading pads corresponding to the electrode terminals formed in the central region of the semiconductor element and its vicinity are electrically connected to external connecting terminal pads formed in the central region on the other side of the wiring board and its vicinity, through the nearest area pad vias encircled by the external connecting terminal pads and passing through the wiring board and the wiring patterns; and a plurality of the loading pads constituting the area pads commonly use one of the area pad vias.
REFERENCES:
patent: 6335566 (2002-01-01), Hirashima et al.
patent: 6734535 (2004-05-01), Hashimoto
patent: 2009/0309210 (2009-12-01), Danno
patent: 10-284538 (1998-10-01), None
Ozawa Takashi
Sato Hitoshi
Potter Roy K
Rankin , Hill & Clark LLP
Shinko Electric Industries Co. Ltd.
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