Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Radiation or energy treatment modifying properties of...
Reexamination Certificate
2011-08-23
2011-08-23
Le, Thao (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Radiation or energy treatment modifying properties of...
C257SE21370
Reexamination Certificate
active
08003477
ABSTRACT:
A method is described for monolithically forming a first memory level above a substrate, the method including: (a) forming a plurality of first substantially parallel, substantially coplanar conductors above the substrate, the first conductors extending in a first direction; (b) forming a plurality of vertically oriented contiguous p-i-n diodes above the first conductors, the contiguous p-in diode comprising semiconductor material crystallized in contact with a silicide, silicide-germanide, or germanide layer; (c) forming a plurality of second substantially parallel, substantially coplanar conductors, the second conductors above the contiguous p-i-n diodes, the second conductors extending in a second direction different from the first direction, each contiguous p-i-n diode vertically disposed between one of the first conductors and one of the second conductors; (d) and forming a plurality of dielectric rupture antifuses, each dielectric rupture antifuse disposed between one of the contiguous p-i-n diodes and one of the first conductors or between one of the contiguous p-i-n diodes and one of the second conductors, wherein the dielectric rupture antifuses comprise dielectric material, the dielectric material having a dielectric constant greater than about 8. Other aspects are provided.
REFERENCES:
patent: 5521423 (1996-05-01), Shinriki et al.
patent: 5693556 (1997-12-01), Cleeves
patent: 5915167 (1999-06-01), Leedy
patent: 5962911 (1999-10-01), Manley
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6100120 (2000-08-01), Yu
patent: 6420215 (2002-07-01), Knall et al.
patent: 6486065 (2002-11-01), Vyvoda et al.
patent: 6515888 (2003-02-01), Johnson et al.
patent: 6525953 (2003-02-01), Johnson
patent: 6534403 (2003-03-01), Cleeves
patent: 6541312 (2003-04-01), Cleeves et al.
patent: 6661691 (2003-12-01), Fricke et al.
patent: 6686646 (2004-02-01), Lee
patent: 6777773 (2004-08-01), Knall
patent: 6853049 (2005-02-01), Herner
patent: 6946719 (2005-09-01), Petti et al.
patent: 6952030 (2005-10-01), Herner et al.
patent: 6952043 (2005-10-01), Vyvoda et al.
patent: 6956278 (2005-10-01), Herner
patent: 7172840 (2007-02-01), Chen
patent: 7176064 (2007-02-01), Herner
patent: 7180123 (2007-02-01), Yeh et al.
patent: 7224013 (2007-05-01), Herner et al.
patent: 7265000 (2007-09-01), Subramanian et al.
patent: 7307013 (2007-12-01), Raghuram et al.
patent: 7314815 (2008-01-01), Ho et al.
patent: 7319053 (2008-01-01), Subramanian et al.
patent: 7405465 (2008-07-01), Herner
patent: 7423304 (2008-09-01), Cleeves et al.
patent: 7575984 (2009-08-01), Radigan et al.
patent: 2003/0003632 (2003-01-01), Cleeves et al.
patent: 2003/0062594 (2003-04-01), Chen
patent: 2004/0016991 (2004-01-01), Johnson et al.
patent: 2004/0232509 (2004-11-01), Vyvoda
patent: 2005/0052915 (2005-03-01), Herner et al.
patent: 2005/0121742 (2005-06-01), Petti et al.
patent: 2005/0158950 (2005-07-01), Scheuerlein et al.
patent: 2005/0221200 (2005-10-01), Chen
patent: 2006/0067117 (2006-03-01), Petti et al.
patent: 2006/0226067 (2006-10-01), Herner et al.
patent: 2006/0249753 (2006-11-01), Herner et al.
patent: 2006/0250836 (2006-11-01), Herner et al.
patent: 2006/0250837 (2006-11-01), Herner et al.
patent: 2007/0002603 (2007-01-01), Cleeves
patent: 2007/0069217 (2007-03-01), Herner
patent: 2007/0072360 (2007-03-01), Kumar et al.
patent: 2007/0087508 (2007-04-01), Herner
patent: 2007/0105284 (2007-05-01), Herner
patent: 2008/0025118 (2008-01-01), Scheuerlein
Herner et al., U.S. Appl. No. 10/326,470, filed Dec. 19, 2002.
International Search Report and Written Opinion of counterpart International Patent Application Serial No. PCT/US2007/023855 mailed May 7, 2008.
Ex parte Quayle Office Action of related U.S. Appl. No. 11/613,151 mailed Mar. 6, 2008.
Notice of Allowance of related U.S. Appl. No. 11/613,151 mailed Sep. 24, 2008.
Hamdy, Esmat et al., “Dielectric Based Antifuse for Logic and Memory Ics”, IEDM 88, (1988), 786-789.
Herner, S. B. et al. “Polycrystalline Silicon/CoSi2 Schottky Diode with Integrated Si02 Antifuse: A Nonvolatile Memory Cell”, Applied Physics Letter, vol. 82, No. 23, Jun. 9, 2003, 4163-4165.
Konakova, R.V. et al., “Ohmic Contacts for Microwave Diodes”, Proc. 22nd International Conference on Microelectronics (MIEL 2000), vol. 2, NIS, Serbia, May 14-17, 2000, (Jan. 1999), 477-480.
Shih, Chih-Ching et al., “Characterization and Modeling of a Highly Reliable Metal-to-Metal Antifuse for High-Performance and High-Density Field-Programmable Gate Arrays”, 1977 IEEE, (Sep. 1997), 25-33.
Wang, Shoue-Jen et al., “High-Perfomance Metal/Silicide Antifuse”, IEEE Electron Device Letter, vol. 13, No. 9, Sep. 1992, 471-472.
Chiang, Steve et al., “Antifuse Structure Comparison for Field Programmable Gate Arrays”, IEDM 92-611, (Apr. 1992), 24.6.1-24.6.4.
Office Action of related U.S. Appl. No. 11/613,151 mailed Feb. 13, 2009.
Office Action of related U.S. Appl. No. 11/560,283 mailed Mar. 24, 2009.
May 6, 2009 Reply to Feb. 13, 2009 Office Action of related U.S. Appl. No. 11/613,151.
Office Action of related U.S. Appl. No. 11/560,289, filed Sep. 18, 2009.
Office Action of related U.S. Appl. No. 11/613,151, filed Sep. 18, 2009.
International Preliminary Report on Patentability of counterpart International Patent Application Serial No. PCT/US2007/023855 dated May 28, 2009.
Jan. 30, 2009 Preliminary Amendment of related U.S. Appl. No. 11/560,289.
Sep. 8, 2008 Reply to Mar. 6, 2008 Ex Parte Quayle Office Action of related U.S. Appl. No. 11/613,151.
Aug. 4, 2009 Preliminary Amendment of counterpart European Patent Application Serial No. 07 840 040.5.
Dec. 10, 2009 Reply to Sep. 18, 2009 Office Action of related U.S. Appl. No. 11/613,151.
Hatalis et al., “Large Grain Polycrystalline Silicon by Low-Temperature Annealing of Low-Pressure Chemical Vapor Deposited Amorphous Silicon Films,”, J. AppI. Phys. 63(7), (Apr. 1, 1988), 2260-2266.
Holloway et al., “Amorphous Ti-Si Alloy Formed by Interdiffusion of Amorphous Si and Crystalline Ti Multilayers,” J. AppI. Phys. 61(4), (Feb. 15, 1987), 1359-1364.
Kim et al., “Oxidation Behavior of a Patterned TiSi2/Polysilicon Stack,” J. Vac. Sci. Technol. B 19(2), (Mar./Apr. 2001), 366-371.
Tang et al., “Twinning in TiSi2-Island Catalyzed Si Nanowires Grown by Gas-Source Molecular-Beam Epitaxy,” Applied Physics Letters, vol. 81, No. 13, (Sep. 23, 2002), 2451-2453.
Tung, “Oxide Mediated Epitaxy of CoSi2 on Silicon,” Appl. Phys. Lett. 68 (24), (Jun. 10, 1996), 3461-3463.
McPherson et al., “Proposed Universal Relationship Between Dielectric Breakdown and Dielectric Constant,” Proceedings of 2003 IEDM, pp. 633-636.
Herner et al., “Effect of Ohmic Contacts on Polysilicon Memory Effect,” Proceedings of Materials Research Society, vol. 864, E5.6.1 (2005).
Office Action Ex Parte Quayle of related U.S. Appl. No. 11/560,283 mailed Aug. 21, 2008.
Notice of Allowance of related U.S. Appl. No. 11/613,151 mailed Jul. 1, 2009.
Notice of Allowance of related U.S. Appl. No. 11/560,283 mailed Sep. 3, 2009.
Jun. 24, 2009 Reply to Mar. 24, 2009 Office Action of related U.S. Appl. No. 11/560,283.
Dec. 22, 2008 Reply to Aug. 21, 2008 Ex Parte Quayle Office Action of related U.S. Appl. No. 11/560,283.
Notice of Allowance of related U.S. Appl. No. 11/560,283 mailed Nov. 2, 2009.
Dec. 17, 2009 Reply to Office Action of related U.S. Appl. No. 11/560,289 mailed Sep. 18, 2009.
Final Office Action of related U.S. Appl. No. 11/613,151 mailed Feb. 23, 2010.
Office Action of related U.S. Appl. No. 11/560,289 mailed Feb. 22, 2010.
Mar. 2, 2010 Office Action of related European Patent Application Serial No. 07 840 040.5.
May 24, 2010 Reply to Final Office Action of related U.S. Appl. No. 11/613,151 mailed Feb. 23, 2010.
May 24, 2010 Reply to Office Action of related U.S. Appl. No. 11/560,289 mailed Feb. 22, 2010.
Final Office Action of related U.S. Appl. No. 11/560,289 mailed Jun. 28, 2010.
Notice of Allowance of related U.S. Appl. No. 11/613,151 mai
Dugan & Dugan PC
Le Thao
SanDisk 3D LLC
LandOfFree
Method for making a P-I-N diode crystallized adjacent to a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for making a P-I-N diode crystallized adjacent to a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making a P-I-N diode crystallized adjacent to a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2648619