Memory system

Details Memory system Memory system

1998-10-09

2000-05-16

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Multiple values

365168, G11C 1600

Patent

active

060645911

ABSTRACT:
A memory system according to the present invention includes a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3, for example, 4) data, wherein the memory cell is operated as an n-level data storing memory cell when the number of times of write-erase sequence is smaller than a predetermined number of times, and the memory cell is operated as an m-level (m is an integer smaller than n, for example, 3) data storing memory cell when the number of times of write-erase sequence has exceeded the predetermined number of times. The number of information items (values) which can be stored in one memory cell is decreased with respect to a predetermined number of times of write-erase sequence. Thus, a memory system including a multi-level data storing memory cell and exhibiting improved durability against write-erase sequence operations is provided.

REFERENCES:
patent: 4357685 (1982-11-01), Daniele et al.
patent: 4718041 (1988-01-01), Baglee et al.
patent: 4811294 (1989-03-01), Kobayashi et al.
patent: 4937787 (1990-06-01), Kobatake
patent: 4943962 (1990-07-01), Imamiya et al.
patent: 4958317 (1990-09-01), Terado et al.
patent: 5105384 (1992-04-01), Noguchi et al.
patent: 5124945 (1992-06-01), Schreck
patent: 5200920 (1993-04-01), Norman et al.
patent: 5218569 (1993-06-01), Banks
patent: 5247480 (1993-09-01), Itoh et al.
patent: 5257225 (1993-10-01), Lee
patent: 5258949 (1993-11-01), Chang et al.
patent: 5293350 (1994-03-01), Kim et al.
patent: 5299162 (1994-03-01), Kim et al.
patent: 5321699 (1994-06-01), Endoh et al.
patent: 5357462 (1994-10-01), Tanaka et al.
patent: 5361277 (1994-11-01), Tanaka et al.
patent: 5369615 (1994-11-01), Harari et al.
patent: 5379256 (1995-01-01), Tanaka et al.
patent: 5388084 (1995-02-01), Itoh et al.
patent: 5414658 (1995-05-01), Challa
patent: 5428569 (1995-06-01), Kato et al.
patent: 5440505 (1995-08-01), Fazio et al.
patent: 5463586 (1995-10-01), Chao et al.
patent: 5467309 (1995-11-01), Tanaka et al.
patent: 5487033 (1996-01-01), Keeney et al.
patent: 5542249 (1996-08-01), Miyamoto et al.
patent: 5555204 (1996-09-01), Endoh et al.
patent: 5557568 (1996-09-01), Miyamoto et al.
patent: 5568439 (1996-10-01), Harari
patent: 5568626 (1996-10-01), Takizawa
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5574879 (1996-11-01), Wells et al.
patent: 5784018 (1998-07-01), Ohmi et al.
patent: 5844841 (1998-12-01), Takeuchi et al.
Tomoharu Tanaka et al., "A Quick Intelligent Program Architecture for 3V-only NAND-EEPROMs", 1992 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 4-6, 1992, pp. 20 and 21.

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