Memory device reference cell programming method and apparatus

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185200, C365S185280, C365S185210, C365S210140, C365S185190

Reexamination Certificate

active

07907444

ABSTRACT:
Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed.

REFERENCES:
patent: 2009/0109743 (2009-04-01), Goda et al.
Sarin, et al.; Cell Deterioration Warning Apparatus and Method; U.S. Appl. No. 11/881,423, filed Jul. 27, 2007; Total pp. 33.
Sarin, et al.; Mitigation of Data Corruption From Back Pattern and Program Disturb in a Non-Volatile Memeory Device; U.S. Appl. No. 11/943,729, filed Nov. 21, 2007, Total pp. 22.

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