Circuit structure for dual resolution design

Details Circuit structure for dual resolution design Circuit structure for dual resolution design

2011-05-24

2011-05-24

Nguyen, Chanh (Department: 2629)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S698000

Reexamination Certificate

active

07948466

ABSTRACT:
A dual resolution circuit for supporting normal resolution display mode and half resolution display mode is disclosed. In the dual resolution circuit, cascaded shift registers are controlled by a group of clock signals to generate intermediate scan signals in response to a start pulse. A normal/reverse scan switch, controlling a normal scan mode and a reverse scan mode, feeds back the intermediate scan signal from one shift register to another shift register. A dual resolution switch switches signal paths of the intermediate scan signals to logic gates. The logic gates perform logic operation on an enablement signal and the intermediate scan signals to generate final scan signals used in dual resolution display modes.

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