FET Logic circuit for the detection of a three level input signa

Details FET Logic circuit for the detection of a three level input signa FET Logic circuit for the detection of a three level input signa

1976-12-20

1978-07-11

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307209, 307214, 307251, 307279, H03K 1908, H03K 1940, H03K 1718, H03K 3353

Patent

active

041004299

ABSTRACT:
A logic circuit in which a first switching means controlled by a first clock pulse signal and a second switching means controlled by a second clock pulse signal are connected in series with each other between the terminals of a first and a second power source, the first and the second clock pulse signals being out of phase from each other, in which an external signal having three levels is applied as an input to the junction point of the first and second switching means, the three-level signal has a first level, i.e. the voltage of the first power source, a second level, i.e. the voltage of the second power source, and an open level, and in which an output is delivered at the junction point. In the logic circuit, when the external input is at the first or the second level, an output corresponding to the input is delivered irrespective of the clock pulses; and when the external input is at the open level, the first level is delivered on the arrival of the first clock pulse while the second level is delivered on the arrival of the second clock pulse, whereby the three levels externally applied can be identified.

REFERENCES:
patent: 3609411 (1971-09-01), Ma et al.
patent: 3812384 (1974-05-01), Skorup
patent: 3845328 (1974-10-01), Hollingsworth
patent: 3950656 (1976-04-01), Sumida et al.
patent: 3969633 (1976-07-01), Paluck et al.

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