Delay locked loop circuit and operational method thereof

Details Delay locked loop circuit and operational method thereof Delay locked loop circuit and operational method thereof

2011-03-29

2011-03-29

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S144000, C327S149000, C327S152000

Reexamination Certificate

active

07915934

ABSTRACT:
A delay locked loop circuit includes a clock buffering block to generate first and second internal clocks corresponding to first and second edges of a source clock in response to a clock buffering control signal, respectively, wherein generation of the second internal clock is controlled by a duty correcting operation terminating signal and a delay locking signal, a delay locking block to compare phases of the first and second internal clocks with those of first and second feedback clocks, respectively, to enable the delay locking signal according to a delay locking and delay the first and second internal clocks as many as times corresponding to the comparison results, respectively, thereby outputting first and second delay locking clocks, a duty correcting block to mix phases of the first and second delay locking clocks, and a first signal generating block to generate the duty correcting operation terminating signal.

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