Electrostatic discharge protection circuit for protecting...

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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C361S111000

Reexamination Certificate

active

07889469

ABSTRACT:
A discharge circuit holds the potential difference between a power supply terminal and reference potential terminal at a predetermined value. The gates of a first pMOSFET and first nMOSFET are connected to an input terminal. A second pMOSFET is connected between the first pMOSFET and power supply terminal, and has a gate to which a first signal is supplied. A second nMOSFET is connected between the first nMOSFET and reference potential terminal, and has a gate to which a second signal is supplied. A detection circuit outputs the first signal which turns on the second pMOSFET and the second signal which turns on the second nMOSFET, while the potential difference is held at the predetermined value. The detection circuit outputs the first signal which turns off the second pMOSFET and the second signal which turns off the second nMOSFET, while the potential difference deviates from the predetermined value.

REFERENCES:
patent: 7154719 (2006-12-01), Krasin
patent: 7595968 (2009-09-01), Hung et al.
patent: 2004/0070901 (2004-04-01), Umeda
patent: 2005/0135033 (2005-06-01), Kitagawa et al.
patent: 2007/0047162 (2007-03-01), Watanabe et al.
patent: 08-275375 (1996-10-01), None
patent: 2001-308200 (2001-11-01), None
patent: 2005-064374 (2005-03-01), None
patent: 2005/094522 (2005-10-01), None
Japanese Office Action for 2007-250133 mailed on Dec. 22, 2009.
K. Watanabe et al, “New Protection Techniques and Test Chip Design for Achieving High CDM Robustness”, EOS/EDS Symposium, pp. 332-338, 2008.

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