Semiconductor memory having error correction circuit

Details Semiconductor memory having error correction circuit Semiconductor memory having error correction circuit

1989-01-12

1991-10-08

Smith, Jerry

Excavating

371 404, 371 112, H03M 1300

Patent

active

050560956

ABSTRACT:
To reduce the number of wirings required between a plurality of memory blocks and a plurality of error correction circuits and thereby reduce the chip area occupied by a semiconductor memory, the present invention provides a semiconductor memory which comprises (1) a plurality of memory blocks (12) for storing information bits, (2) another memory block (13) for storing test bits, (3) a plurality of multiplexers (26) disposed at the respective output sections of the memory blocks (12), (4) a plurality of parity test circuits (27) each responding to bit information for a parity test which is generated from one output from the corresponding one of the multiplexers (26), (5) a syndrome bus (22) responding to both the respective outputs of the parity test circuits (26) and the output of the another memory block (13), and (6) a plurality of error correction circuits (21) each responding to both output data (28) generated from the other output of the corresponding one of the multiplexers (26) and a syndrome generated from the syndrome bus (22).

REFERENCES:
patent: 3851306 (1974-11-01), Patel
patent: 4625313 (1986-11-01), Springer
patent: 4651321 (1987-03-01), Woffinden et al.
patent: 4763329 (1988-08-01), Green
patent: 4780875 (1988-10-01), Sakai
patent: 4817095 (1989-03-01), Smelser et al.

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