Delay fault testing method and apparatus

Details Delay fault testing method and apparatus Delay fault testing method and apparatus

1989-06-09

1991-10-08

Smith, Jerry

Excavating

371 221, G06F 1100

Patent

active

050560948

ABSTRACT:
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously. This architecture allows propagation delays between devices to be determined. A driving device (264) toggles its input on a first clock edge. On a subsequent clock edge, the receiving circuit (266) samples its input. The sampled input may be scanned out and compared to the toggled value to determine whether the signal propagated between the first and second clock edges.

REFERENCES:
patent: Re31056 (1982-10-01), Chau et al.
patent: 3873818 (1975-03-01), Barnard
patent: 3976940 (1976-08-01), Chau et al.
patent: 4066882 (1978-01-01), Esposito
patent: 4146835 (1979-03-01), Chnapto et al.
patent: 4777616 (1988-10-01), Moore et al.
patent: 4899273 (1990-02-01), Omoda et al.
patent: 4937826 (1990-06-01), Cheewala et al.

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