Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-06-14
2011-06-14
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S119000, C716S126000, C716S134000
Reexamination Certificate
active
07962875
ABSTRACT:
A circuit designing method for a semiconductor integrated circuit, the circuit having a clock control circuit and leaves to which clock signals are propagated through the clock control circuit, has detecting a clock signal producing point where a clock signal is to be produced and an operational mode setting point where an operational mode setting signal for setting an operational mode is to be imparted, using a netlist and a cell library, setting a clock signal and a name of the clock signal at the clock signal producing point, setting an operational mode setting signal suitable for a desired operational mode at the operational mode setting point, propagating the clock signal and the operational mode setting signal, and extracting signals being propagated to the leaves.
REFERENCES:
patent: 5452239 (1995-09-01), Dai et al.
patent: 6321366 (2001-11-01), Tseng et al.
patent: 6615392 (2003-09-01), Nadeau-Dostie et al.
patent: 6785873 (2004-08-01), Tseng
patent: 6959426 (2005-10-01), Xiang et al.
patent: 6978429 (2005-12-01), Yoshida et al.
patent: 7185295 (2007-02-01), Park et al.
patent: 7299433 (2007-11-01), Clement et al.
patent: 7478349 (2009-01-01), Hayles et al.
patent: 7610569 (2009-10-01), Park
patent: 7653849 (2010-01-01), Tabatabaei
patent: 7770139 (2010-08-01), Arsovski et al.
patent: 2002/0152060 (2002-10-01), Tseng
patent: 2003/0171908 (2003-09-01), Schilp et al.
patent: 2004/0153978 (2004-08-01), Xiang et al.
patent: 2004/0250224 (2004-12-01), Clement et al.
patent: 2005/0149895 (2005-07-01), Toubou
patent: 2005/0216247 (2005-09-01), Ikeda et al.
patent: 2006/0117274 (2006-06-01), Tseng et al.
patent: 2006/0253823 (2006-11-01), Matsumura et al.
patent: 2007/0113209 (2007-05-01), Park et al.
patent: 2007/0180413 (2007-08-01), Park
patent: 2009/0177445 (2009-07-01), Capps et al.
patent: 2006-085595 (2006-03-01), None
Kabushiki Kaisha Toshiba
Kik Phallaka
Turocy & Watson LLP
LandOfFree
Method, apparatus and program for designing circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method, apparatus and program for designing circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, apparatus and program for designing circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2629538