Method of fabricating an integrated circuit with stress...

Details Method of fabricating an integrated circuit with stress... Method of fabricating an integrated circuit with stress...

2011-04-26

2011-04-26

Tran, Minh-Loan T (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S638000, C257S640000, C257SE27108, C438S740000

Reexamination Certificate

active

07932542

ABSTRACT:
A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.

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