Congestion aware pin optimizer

Details Congestion aware pin optimizer Congestion aware pin optimizer

2011-06-28

2011-06-28

Levin, Naum (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S118000, C716S130000

Reexamination Certificate

active

07971174

ABSTRACT:
A circuit design process for the reduction of routing congestion is described. This process includes a block placement operation, an initial pin optimization for the block placement, and global routing based upon the initial pin optimization. Congestion data is generated from the global routing and, in an automated process, the pins are re-optimized, based upon the congestion data. This process can be used as part of a custom layout design process, for example.

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