Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Patent
1994-01-12
2000-05-16
Wu, Xiao
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
345 95, 345 89, 345211, G09G 336
Patent
active
060643617
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a method of driving an LCD (liquid crystal display) which performs multi-gradation display, more in detail, to a method of driving an LCD which performs multi-gradation display based on an image information quantized by an A/D converter (analog-digital converter).
BACKGROUND TECHNOLOGY
Recently a digital signal processing has been generally applied to an image display. For example, when the analog signal of TV, etc. is subjected to an A/D conversion, there appears a false outline of a displayed image since the continuity of gradation is lost (quantization noise). Many liquid crystal TVs which employ LCDs as display elements also use A/D converters. Passive matrix panels for displaying moving pictures generally employ a method of subjecting a luminance signal to A/D conversion and thereafter converting the resulting digital signal into a pulse width, and it is known that active matrix panels employing MIM elements can also use a similar method (e.g., refer to Japanese Patent Publication No. 63 - 6855).
Many liquid crystal TVs employ a 4 - bit A/D converter for the purpose of miniaturization or securing portability. The number of gradations which can be displayed by 4 - bit data, however, is as few as 16, so that quantization noise is conspicuous.
FIG. 16 is a block diagram exemplifying a system for improving image quality using a dither method. In the system, a TV signal is input to the input terminal IN of a 4 - bit A/D converter 1, which supplies an A/D converted 4 - bit data to a memory 21 in a signal electrode driving circuit 2.
A multiplexer 3 comprises an upper switch 31 for switching to the upper reference potentials Vt1 or Vt2 and a lower switch 32 for switching to the lower reference potentials Vb1 or Vb2 at the input sides thereof, the switches 31 and 32 being coupled to the upper reference potential input terminal Vrt and the lower reference potential input terminal Vrb of the 4 - bit A/D converter 1 respectively at the output sides thereof.
A clock .phi.1 produced by a controller 4 is supplied to the multiplexer 3 for controlling the switches 31 and 32 in liaison with each other.
The controller 4 also supplies a signal group .phi.4 including a start signal for timing the start of scanning, a clock for timing the successive shift of a selected pulse, etc. to a scanning electrode driving circuit 5.
Moreover, the A/D converter 1 and the signal electrode driving circuit 2 receive a signal group .phi.3 which is formed mainly on the basis of a horizontal synchronous signal, including a (data sampling clock, a shift clock which forms addresses in the memory 21, a latch clock which transfers data within the memory 21, a signal for timing a pulse width modulation, etc.
The signal electrode driving circuit 2 comprising the memory 21 and a pulse width modulation circuit 22 is coupled to each signal electrode of a liquid crystal panel 6 at each output terminal thereof and a scanning electrode driving circuit 5 is coupled to each scanning electrode of the liquid crystal panel 6 at each out put terminal thereof.
In FIG. 16, the memory 21 transfers all the data to the pulse width modulation circuit 22 after completion of successively reading the 4 - bit data in a cycle of horizontal scanning.
In a display method employing a common line sequential scanning, the A/D converter 1 quantizes a TV signal into 4 - bit data during a first horizontal scanning period and successively stores the same in memory 21. During a second horizontal scanning period, at first the data read by the latch clock of the clock group .phi.3 of the controller 4 is transferred to the pulse width modulation circuit 22.
The pulse width modulation circuit 22 subjects the transferred data to pulse width modulation and supplies the same to the signal electrodes of the liquid crystal panel 6. At that time, the scanning electrode driving circuit 5 supplies selective potentials to corresponding electrodes so as to apply a gradation driving signal to desired pixels together with the waveform produ
REFERENCES:
patent: 3938136 (1976-02-01), Kawakami
patent: 4921334 (1990-05-01), Akodes
patent: 5196738 (1993-03-01), Takahara et al.
patent: 5216417 (1993-06-01), Honda
Citizen Watch Co. Ltd.
Wu Xiao
LandOfFree
Method of driving LCD does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of driving LCD, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of driving LCD will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-262517