Delay data setting circuit and method

Details Delay data setting circuit and method Delay data setting circuit and method

1991-05-31

1994-04-19

Canney, Vincent P.

Excavating

371 221, G01R 3128

Patent

active

053053290

ABSTRACT:
Pins of an IC under test are classified into pin groups according to the delay time to be set for a test clock for each pin, and a table of pin group data, which has, at a bit position corresponding to each bit, a "1" "0" which indicates that the pin belongs to each pin group, is stored in a pin group table memory. The bit positions of the logical values "1", indicating that the pins belong to the pin group, in each pin group data read out from the pin group table memory are sequentially encoded by a priority encoder in an ascending (or descending) order and the delay data is provided to a delay data memory. The delay time data common to all the pins belonging to the pin group provided from a tester processor is written into sequentially specified addresses, by which the delay time data for all of the pins can be written into the delay data memory from the tester processor in a short time.

REFERENCES:
patent: 4493079 (1985-01-01), Hughes, Jr.
patent: 4692920 (1987-09-01), Tannhaeuser et al.
patent: 4730318 (1988-03-01), Bogholtz et al.

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