Stacked structures and methods of fabricating stacked...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part

Reexamination Certificate

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C257SE23145, C438S455000, C438S586000, C438S598000, C438S618000, C438S622000

Reexamination Certificate

active

07956448

ABSTRACT:
A stacked structure includes a first substrate bonded to a second substrate such that a first pad structure of the first substrate contacts a second pad structure of the second substrate. A transistor gate is formed over the second substrate, and a first conductive structure extends through the second substrate and has a top surface that is substantially planar with a top surface of the second substrate. An interlayer dielectric (ILD) layer is disposed over the transistor gate, and a passivation layer is disposed over the ILD layer and includes a second pad structure that makes electrical contact with the second conductive structure. The ILD layer includes at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate. A second conductive structure is disposed in the ILD layer and is at least partially disposed over a surface of the first conductive structure.

REFERENCES:
patent: 6642081 (2003-11-01), Patti
patent: 6897125 (2005-05-01), Morrow et al.
patent: 2004/0232554 (2004-11-01), Hirano et al.
patent: 2007/0007595 (2007-01-01), Hirano et al.
patent: 2008/0020488 (2008-01-01), Clevenger et al.
patent: I234866 (2005-06-01), None
patent: I257144 (2006-06-01), None
Official Action issued Sep. 15, 2010 in counterpart Taiwan application.

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