Static information storage and retrieval – Floating gate – Disturbance control
Reexamination Certificate
2011-03-29
2011-03-29
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Floating gate
Disturbance control
C365S185180, C365S185250, C365S185280
Reexamination Certificate
active
07916532
ABSTRACT:
A memory array and method for performing a write operation in a memory array that eliminates parasitic coupling between selected and unselected bitlines and protects memory cells on unselected bitlines. A memory array (100); has a plurality of memory cells (148, 150,152, 154), each of which is coupled to a unique array bitline (104, 106, 108,110). A unique recovery transistor (138; 140, 142, 144) coupled to each array bitline (104, 106, 108, 110). The recovery transistors (140, 144) on odd bitlines (140, 144) are coupled to a first and second voltage (128, 144), while the recovery transistors on even bitlines are coupled, to a first and third voltage (128, 126). During a write operation, each recovery transistor coupled to an unselected bitline is active during a write operation and a recovery operation, while each recovery transistor coupled; to selected bitline is active during a recovery operation. The first voltage (128) is sufficient to prevent parasitic coupling between the selected bitlines and the unselected bitlines during the write operation.
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Curry Duncan
Lambrache Emil
Pang Richard F.
Atmel Corporation
Ho Hoai V
Schwegman Lundberg & Woessner, P.A.
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