Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-08-07
2001-11-20
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110
Reexamination Certificate
active
06320792
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a row decoding circuit and method for an electrically programmable semiconductor non-volatile memory.
More particularly, the invention relates to a row decoding circuit for a semiconductor non-volatile storage device which is programmable and erasable electrically and of the type including a matrix of memory cells laid out as rows and columns of cells and divided into sectors, the circuit being input row decode signals and supply voltages in order to drive an output stage which incorporates a complementary pair of high-voltage MOS transistors, respectively of pull-up and pull-down, connected to form an output terminal for connection to the rows in a sector of the matrix.
2. Discussion of the Related Art
As is well known, read-only memories of the flash type have made substantial inroads as non-volatile memories because they can combine the advantages of high density that typify EPROMs with the capability of being programmed and erased electrically in the same way as EEPROMs.
Memories of this kind are constructed as matrices of cells, wherein each cell includes a floating gate transistor. Each transistor has a drain region and a source region which are formed on a semiconductor substrate and separated by a channel region.
A floating gate is formed over the substrate and isolated therefrom by a thin layer of gate oxide. A control gate is coupled capacitively to the floating gate by means of a dielectric layer. Metallic electrodes are arranged to contact the drain, source, and control gate such that predetermined voltage values can be applied to the memory cells.
The cell matrix is laid out into rows, or word lines, and columns, or bit lines. The cells of one word line share the electrical line that drives their respective control gates, while the cells of one bit line have their drain terminals in common.
By applying suitable voltage values to the cell terminals, the amount of the charge present in the floating gate can be varied, and since the floating gate has a high impedance toward any other terminals of the cell, the charge stored in it can be maintained indefinitely, even when the supply is cut off to the circuit in which it is included.
The operation whereby a charge is stored into the floating gate is called “programming” and consists of biasing the drain terminal and control gate at a predetermined higher value than the potential of the source terminal.
This programming of the individual cells is carried out by a hot electron injection process which allows electrons to become trapped inside the floating gate when the control gate is applied approximately 12 volts, with the source terminal being connected to ground and the drain terminal held at a drain voltage of about 5.5 volts.
In order to erase a flash memory cell, its source terminal is applied a voltage approximately equal to the supply voltage Vcc, the drain terminal is held floating, and the control gate is either led to ground or biased with a negative voltage.
In the field of application of the present invention, the negative voltage being applied to the decoding circuit during the steps of erasing the contents of the memory cells requires appropriate control.
A prior technical solution for properly controlling this negative voltage is described in U.S. Pat. No. 5,126,808, (hereinafter the “'800 Patent”) which discloses a structure of a flash EEPROM matrix and respective erasing circuitry by the sector.
While being in many ways advantageous, this prior solution is not devoid of drawbacks, as detailed herein below.
The row decoding circuit structure described in the '808 Patent provides for a final stage which includes a pull-up transistor and a pull-down transistor placed on opposite sides of an output terminal being connected to the word lines of the memory matrix.
Connected between the output terminal and the pull-down transistor is a P-channel transistor whose control terminal is applied a negative voltage during the step of erasing the memory cells.
This negative voltage must be supplied from a dedicated negative charge pump to allow the word lines to be driven to ground during the erasing step.
The provision of such a charge pump unavoidably involves some consumption of circuit area as well as of current, since the pump must be kept under power even while in the standby state to ensure a fast time of access to the memory upon exiting the standby state.
In addition, the input stage of the decoding circuit described in the '808 Patent includes a NAND portion incorporating P-channel transistors, which burdens the circuit construction.
Finally, no provision is made in this prior solution for an accurate regulation of the row decoding supply voltages to make the unselected sectors of the matrix fully independent of the operations being performed on a given selected sector.
An object of the present invention is to provide a novel row decoding circuit and method which have such constructional and functional features as to overcome the aforementioned drawbacks of conventional solutions.
SUMMARY OF THE INVENTION
An embodiment of the invention is directed to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of a type having a matrix of memory cells laid out as rows and columns. The matrix is divided into sectors such that each sector has a corresponding plurality of rows. The row decoding circuit includes an input stage that receives input row decode signals and supply voltages, and an output stage that is driven by the input row decode signals and the supply voltages. The output stage has a complimentary pair of high-voltage moss transistors including a pull up transistor and a pull down transistor. The pull up and pull down transistors are connected to form an output terminal. The output terminal is connected to a plurality of rows corresponding to a sector of the matrix. The output stage further includes a moss transistors of the P channel depletion type with enhanced gate oxide. The moss transistor is disposed between the output terminal and the pull down transistors.
Another embodiment of the invention is directed to a row decoding method for an electrically programmable and erasable semiconductor non-volatile memory of a type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors. The memory receives as inputs row decode signals and supply voltages in order to drive an output stage incorporating a complimentary pair of high voltage moss transistors of the pull up and pull down type, respectively, which are connected to form an output terminal connected to rows of one sector of the matrix. The method includes a step of operating a plurality of local supply switches. Each local supply switch is associated with a decoding circuit of a matrix sector.
The features and advantages of the circuit and the method of the present invention will be apparent from the following detailed description of embodiments thereof, given by way of non-limitative examples with reference to the accompanying drawings.
REFERENCES:
patent: 5371705 (1994-12-01), Nakayama et al.
patent: 5400276 (1995-03-01), Takeguchi
patent: 5463583 (1995-10-01), Takashina
patent: 5587960 (1996-12-01), Ferris
patent: 5631597 (1997-05-01), Akaogi et al.
patent: 5644530 (1997-07-01), Gautlier
patent: 5828600 (1998-10-01), Kato et al.
European Search Report from European Patent Application 96830174.7, filed Mar. 29, 1996.
IEICE Transactions On Electronics, vol. E77-c, No. 5, Mar. 1994, Tokyo JP, pp. 791-798, Atsumi, et al. “A 16 MB Flash EEPROM With A New Self Data Refresh Scheme For A Sector Erase Operation”.
Cane Marcello
Caser Fabio Tassan
Sali Mauro
Hoang Huan
Morris James H.
SGS-Thomson Microelectronics S.r.l
Wolf Greenfield & Sacks P.C.
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