Structure and fabrication process of silicon on insulator wafer

Details Structure and fabrication process of silicon on insulator wafer Structure and fabrication process of silicon on insulator wafer

2001-01-04

2001-11-27

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

C438S977000, C148SDIG001

Reexamination Certificate

active

06323110

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the structure and fabrication process of silicon on insulator (SOI) wafers for making the integrated circuits (ICs) thereon. More particularly, this invention relates to the structure and fabrication process of SOI wafers for making integrated circuits (ICs) thereon which has larger volume for current sink and has reduced susceptibility to electric static discharge (ESD) and electric over stress (EOS).
2. Description of the Prior Art
Even though the technology for making the silicon on insulator (SOI) wafer has demonstrated significant progress recently such that integrated circuit (IC) devices of high speed can be fabricated thereon with less complicate processes. However, widespread application of this technology is still limited by several technical difficulties. The primary major concern for IC devices made on SOI wafer is their susceptibility to damages caused by electric static discharge (ESD) or electric over stress (EOS). The wafers employed in IC devices fabrication generally comprise a thin layer on the top surface of the wafers for the processing and fabrication of various IC circuits. This thin device layer is then supported by a substrate composed mostly of dielelctric materials forming a much thicker bulk region. The silicon on insulator (SOI) wafer provides an insulating layer, e.g., a silicon dioxide (SiO
2
) layer, which insulates and separates the bulk region of the substrate from the the device region.
FIG. 1
shows a cross sectional view of a conventional SOI wafer which includes a silicon or epitaxy layer
10
, an insulating layer
20
and a bulk silicon region
30
. Generally, the silicon or epitaxy layer
10
is generally a device region with a thickness ranging from approximately 500 to 20,0000 angstroms. The insulating layer, e.g., an SiO
2
layer, is approximately 1,000 to 10,000 angstroms in thickness. The bulk region
30
supports the whole structure which can be a polysilicon region to maintain the cost of fabrication at a low level.
There are several advantages provided by the technique of fabricating IC devices on the SOI wafers over the general IC devices made on bulk substrate. First, the parasitic effects between the devices and the substrate, especially the parasitic capacitance, can be eliminated. Since this parasitic capacitance increases with the substrate doping and that the doping concentration is greatly increased in modem sub-micron devices, this SOI advantage becomes more important for modem submicron devices. Secondly, another parasitic problem, i.e., the latchup, which often becomes more severe as the dimension of the IC devices becomes smaller, can also be avoided by fabricating IC devices on the SOI wafer. The SOI wafers thus provide a supporting structure more advantageous for fabricating IC devices of smaller dimension with improved integration density and high speed performance.
However, since the bulk material of an SOI wafer is now separated by the insulating layer from the device region, electrically the bulk material of the substrate is no longer part of the device integration. The use of substrate for defining a constant electric potential or using the well taps in electric contact with the substrate to stabilize channel threshold voltages (V
T
) for the IC devices are no longer feasible. Furthermore, the traditional design of employing the large volume of the well in the bulk region as a current sink for sudden high density current to prevent the occurrence of ESD or ESO is also not achievable on the SOI wafer. The IC devices on the SOI wafers may become very susceptible to ESD or EOS damages. This concern becomes more critical as the IC circuits are fabricated with smaller dimension and more sensitive and susceptible to spikes of high density currents. Therefore, unless this technical problem is resolved, even with the significant advantages and recent technical progress made in SOI wafers process, application of the SOI wafers for IC device fabrication is still greatly limited.
Besides the ESD and EOS problems, the IC devices on SOI wafer have another difficulty due to the fact that the electric potential in the channel region of the transistor area is floating as it is now insulated from the bulk substrate by the underlying insulator film. In a conventional bulk transistor, electrical connection can be easily made via the substrate to a body node and the relatively fixed bias of a body node provides a stable threshold voltage relative to the drain to source voltage. However, in most SOI transistors, the undepleted volume within the body region underneath the gate electrode now functions as a body node. The electric potential of the body node is important for the determination of the threshold voltage of an IC device. However, the volume near the body node under the channel region has now become electrically floating as the volume is insulated from the substrate by the underlying insulating dioxide layer. The effective threshold of the transistors may be adversely affected which causes great uncertainty in designing and controlling operational characteristics of the transistor devices fabricated on the SOI wafers.
The transistor fabricated on an SOI structure further encounter another problem commonly recognized as the parasitic ‘back channel’ effect. It is caused by a ‘back channel transistor’ configuration where the substrate functions as a gate and the insulator film underlying the transistor functions as a gate dielectric. This back channel may cause a drain to source leakage path along the body node underneath the gate channel near the interface with the insulating film. Furthermore, a capacitive coupling is formed between the drain and the source over the dielectrically insulated body node which often bias the potential of the body node thus affecting the threshold voltage as well. All the above described factors may cause voltage shifts and add to greater uncertainties in designing and stabilizing the gate threshold voltage for the IC devices to be fabricated on the device layer n an SOI wafer.
Several techniques are proposed in order to overcome this difficulty. Houston et al. disclose in U.S. Pat. No. 5,185,280, entitled ‘Method of fabricating a SOI transistor with Pocket Implant and Body-to-Source (BTS) Contact’, a SOI MOS transistor that has an implanted region of the same conductivity type as the body underneath one or both of the extended drain and source portions of the drain and the source with and without a BTS contact or a general body contact. The purpose is to use the ‘pocket implants’ to enhance the gate threshold voltage by reducing the back gate current. Ohmic connection between the source and the body is then made by silicidation.
The transistor as proposed by Houston et al. may have an enhanced threshold voltage, however, the difficulties caused by the floating potential of the body node is not completed resolved. By the use of the pocket implants, the voltage fluctuation at the body node may be reduced, however, as the small volume of the ‘body node’ underneath the gate channel is still insulated, its voltage is still floating. This floating voltage can not be conveniently stabilized and thus becomes easily biased by the substrate voltage due to the ‘back channel’ transistor effect and any other voltage changes near the transistor. The threshold voltage is therefore not definitely controllable in the disclosed configuration. Additionally, the technique disclose by Houston et al. has to be implemented with more complex designs and fabrication processes which have to be carries out in the very thin device layer and may greatly increase the cost of the devices.
Several U.S. Patents, including U.S. Pat. No. 4,899,202 entitled ‘High Performance Silicon-on-insulator Transistor with Body Node to Source Node Connection’ (Issued on Feb. 6, 1990 to Blake et al.), U.S. Pat. No. 4,906,587 entitled ‘Making A Silicon-on-insulator Transistor with Selectable Body Node to Source Node Connection’ (Issued on Mar. 6, 1990 to

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