Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-11-03
2001-02-13
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S217000
Reexamination Certificate
active
06188259
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to digital sequential logic circuits. More particularly, the present invention presents a self-resetting flip-flop for use in high-speed electronics.
2. The Background Art
In high speed digital electronics, it is often desirable to have the output of one functional unit isolated from the input of the other, except at certain times.
FIG. 1
is a prior art example of isolating one functional unit from another using flip-flips.
Referring to
FIG. 1
, system
10
includes a device
12
which is coupled to an address bus
14
. Memory manager
16
is coupled to address bus
14
and memory
18
, and includes row circuitry
20
and column circuitry
22
. Row circuitry
20
and column circuitry
22
each have similar circuitry which is used to access the memory cells corresponding to an address on the address bus. Thus, flip-flops
24
, predecoder
26
and decoder
28
are each present in row circuitry
20
and column circuitry
22
.
In order to provide the highest level of data throughput to and from memory, it is desirable to isolate activity on an address bus from address decoders, except at specific times when the address data is generally held to be valid.
In order to isolate the address bus from the decoder a flip-flop is often provided between the bus and the decoder. As is known by those of ordinary skill in the art, a flip-flop takes a data state present on its input and latches that data to its output, on the rising edge of a clock cycle.
In some cases, it is appropriate to reset the flip-flop output to a known “safe” state so that functional units using the data supplied by the flip-flop will always be receiving valid data.
Although prior art flip-flops are suitable for their intended purpose of providing a measure of isolation between the incoming data lines and the output lines, the reset mechanisms present in these flip-flops are often not fast enough to meet the demands of high speed electronics. It would therefore be beneficial to provide a flip-flop having a fast reset mechanism.
SUMMARY OF THE INVENTION
The present invention is a dynamic flip-flop circuit with a set-reset shut-off mechanism which comprises a data input stage, an output stage, a reset circuit and a shut-off circuit. The data input stage has a clock input, a data input and an input stage output. The output stage has an input coupled to the input stage output, and generates at least one data output. The reset circuit has a reset input coupled to the data output and has a reset output coupled to the output stage, which resets the logic state of the output stage to a predetermined desired condition. The shutoff circuit receives the clock input and the input stage output and generates a shut-off circuit output signal which is presented to the data input stage to disable the data input stage after a predetermined time period.
In operation, input data signals and clocking signals are communicated to a data input stage. When the clocking signal is high, the circuit is in the evaluation phase and the data input stage provides data and the complement of data to be submitted to an output stage which generates Q and Q! output pulses.
The Q and Q! output are also communicated to a reset circuit. The reset circuit operates to ensure that a desired quiescent state is achieved and “resets” the output stage.
The shut-off circuit performs the function of disabling the data signal using the leading edge of the clocking signal. The dynamic flip-flop circuit permits input data to be sampled for a short time interval defined by the clock signal going high and a shut-off circuit output going low.
This particular self reset flip-flop with a self shut-off circuit reduces hold time for the data inputs and provides reduced clock loading. Additionally, the flip-flop circuit provides more robustness and better noise immunity than previous self reset flop designs. Finally, the self reset flip-flop with shut-off circuit is a simple design which occupies a small area.
REFERENCES:
patent: 5461649 (1995-10-01), Bailey et al.
patent: 5898640 (1999-09-01), Ben-Meir et al.
Amir Chaim
Ngo Heip P.
Sierra Patent Group Ltd.
Sun Microsystems Inc.
Tran Toan
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