Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
1998-09-29
2001-11-27
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S106000, C029S852000, C174S258000, C361S751000
Reexamination Certificate
active
06323096
ABSTRACT:
BACKGROUND OF THE INVENTION
In one form of high density interconnect (HDI) circuit module, an adhesive-coated polymer film overlay having via openings covers a substrate which can support integrated circuit chips in chip wells. The polymer film provides an insulated layer upon which is deposited a metallization pattern for interconnection of substrate metallization and/or individual circuit chips through the vias. Methods for performing an HDI process using overlays are further described in Eichelberger et al., U.S. Pat. No. 4,783,695, issued Nov. 8, 1988, and in Eichelberger et al., U.S. Pat. No. 4,933,042, issued Jun. 12, 1990. Generally a plurality of polymer film overlays and metallization patterns are used.
In another form of circuit module fabrication, as described by Cole et al., U.S. Pat. No. 5,527,741, issued Jun. 18, 1996, a method for fabricating a circuit module includes using a flexible interconnect layer having a metallized base insulative layer and an outer insulative layer. At least one circuit chip having chip pads is attached to the base insulative layer and vias are formed in the outer and base insulative layers to expose selected portions of the base insulative layer metallization and the chip pads. A patterned outer metallization layer is applied over the outer insulative layer extending through selected ones of the vias to interconnect selected ones of the chip pads and selected portions of the base insulative layer metallization.
Fabrication of thin film resistors, capacitors, and inductors is described in
The Handbook of Thin Film Technology
, chs. 18 and 19 (Maissel and Glang eds., McGraw-Hill Book Company 1970, 1983 Reissue).
Commonly assigned Wojnarowski et al., “Thin Film Resistors on Organic Surfaces,” U.S. Pat. No. 5,675,310, filed Dec. 5, 1994, describes a method for fabricating a thin film resistor comprising: applying a tantalum nitride layer over an organic dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on th tantalum nitride layer. After patterning the metallization layer, the resistance value between the first and second portions of the metallization layer can be determined and compared to a predetermined resistance value, and at least one of the first and second portions can be trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value. Preferably, the tantalum nitride layer comprises a hexagonal closed packed Ta
2
N structure and the dielectric layer comprises a polyimide. Commonly assigned Wojnarowski et al., “Application of Thin Film Electronic Components on Organic and Inorganic Surfaces,” U.S. Pat. No. 5,683,928, filed Dec. 5, 1994, describes a method for the manufacture of precision electronic components such as resistors, inductors, and capacitors, for example, on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by changing the physical length of an inductor coil or resistor lead, or by changing the capacitor plate area.
Commonly assigned Saia et al., “Structure and Fabrication Method for Thin Film Capacitors,” U.S. Pat. No. 5,736,448, filed Dec. 4, 1995, describes structures and methods of incorporating thin film capacitors on polymer layers such as those in laminated high density interconnect (HDI) multichip modules and in flexible interconnect layers with good adhesion. The capacitors can be fabricated using interconnect metallization (titanium coated with copper coated with titanium) as the lower capacitor plate, amorphous hydrogenated carbon (commonly referred to as diamond-like carbon or DLC) as the capacitor dielectric material, and a sputtered metallization layer as the upper capacitor plate. Good adhesion of DLC to a capacitor plate can be obtained with a thin molybdenum adhesion layer and a pressure graded DLC deposition using an organic precursor including oxygen. The integral capacitors can be fabricated using a fabrication process compatible with conventional HDI and flexible interconnect materials.
SUMMARY OF THE INVENTION
It would be advantageous to have an efficient, cost-effective, and space-saving fabrication method and structure for integration of passive components on flexible interconnect layers. It would also be advantageous to have a framed structure for distortion-free deposition and fabrication of such flexible interconnect layers and to have a composite thin film structure from which interconnect areas and passive components can be fabricated.
In the present invention, a flexible film structure has thin film resistors, capacitors, and inductors fabricated thereon and integrated with film metallization. Tantalum nitride (Ta
2
N) films can be used as adhesion primer layers for copper metallization or as thin film resistor material, and DLC or tantalum oxide (Ta
2
O
5
) can be used for fabrication of the thin film capacitors.
Briefly, according to one embodiment of the present invention, for example, a method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode. In one embodiment, during application and patterning of the layers, the dielectric film is efficiently maintained in a rigid form without distortion by use of a frame.
In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide. If the resistor and metallization layers are applied over both surfaces of the dielectric film, passive components can be fabricated on both surfaces of the dielectric film. The dielectric film can have vias therein with the resistor and metallization layers extending through the vias. A circuit chip can be attached and coupled to the passive components by metallization patterned through vias in an additional dielectric layer.
REFERENCES:
patent: 4677042 (1987-06-01), Kato et al.
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 4788767 (1988-12-01), Desai et al.
patent: 4835704 (1989-05-01), Eichelberger et al.
patent: 4894115 (1990-01-01), Eichelberger et al.
patent: 4897153 (1990-01-01), Cole et al.
patent: 4933042 (1990-06-01), Eichelberger et al.
patent: 4937133 (1990-06-01), Watanabe et al.
patent: 5042945 (1991-08-01), Shibata et al.
patent: 5108825 (1992-04-01), Wojnarowski et al.
patent: 5159239 (1992-10-01), Ekkelboom et al.
patent: 5161093 (1992-11-01), Gorczyca et al.
patent: 5172304 (1992-12-01), Ozawa et al.
patent: 5338975 (1994-08-01), Cole, Jr. et al.
patent: 5353195 (1994-10-01), Fillion et al.
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5370766 (1994-12-01), Desaigoudar et al.
patent: 5422513 (1995-06-01), Marcinkiewicz et al.
patent: 5436062 (1995-07-01), Schmidt e
Cole Herbert Stanley
Durocher Kevin Matthew
Saia Richard Joseph
Agosti Ann M.
Bowers Charles
Breedlove Jill M.
General Electric Company
Smoot Stephen W.
LandOfFree
Method for fabricating a flexible interconnect film with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating a flexible interconnect film with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a flexible interconnect film with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2615962