Operational amplifier

Details Operational amplifier Operational amplifier

1999-12-27

2001-11-13

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S253000

Reexamination Certificate

active

06316999

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an operational amplifier, and more particularly to an operational amplifier capable of suppressing occurrence of overshootor undershoot to the minimum.
2. Description of the Prior Art
As an operational amplifier which can handle input and output in a wide range and drive a large load, up to now, there has been a technique disclosed in Japanese Patent Publication No.Hei 9-93,055 by the present inventors.
An operational amplifier disclosed in Japanese Patent Publication No.Hei 9-93,055 is described with reference to FIG.
10
. The operational amplifier is provided with an input stage K
1
, a driving stage K
2
and an output stage K
3
.
First, the composition of the input stage K
1
of the operational amplifier is described. The input stage K
1
of the operational amplifier is provided with P channel field effect transistors (FETs) M
1
and M
2
, N channel FETs M
5
and M
6
, a P channel FET for constant current source M
41
, an N channel FET for constant current source M
42
, N channel FETs M
3
and M
9
, N channel FETs M
4
and M
10
, and P channel FETs M
7
and M
8
. The P channel FETs M
1
and M
2
, whose sources are commonly connected to each other and whose gates are respectively to signal input terminals
1
and
2
, form a differential transistor couple. The N channel FETs M
5
and M
6
, whose sources are commonly connected to each other and whose gates are respectively to signal input terminals
1
and
2
, form a differential transistor couple. The P channel FET for constant current source M
41
is connected between the sources of the P channel FETs M
1
and M
2
commonly connected to each other and a high level side power source terminal
5
.
The N channel FET for constant current source M
42
is connected between the sources of the N channel FETs M
5
and M
6
commonly connected to each other and a low level side power source terminal
4
. In the N channel FET M
3
, its gate and drain are connected to the drain of the P channel FET M
1
and its source is connected to the low level side power source terminal
4
. In an N channel FET M
9
, its drain is connected to the connection point of the drain of the N channel FET M
6
and the drain of the P channel FET M
7
, and its source is connected to the low level side power source terminal
4
. The N channel FETs M
3
and M
9
form a first current mirror circuit. In an N channel FET M
4
, its drain and gate are connected to the drain of the P channel FET M
2
and its source is connected to the low level side power source terminal
4
.
In an N channel FET M
10
, its drain is connected to the connection point of the drain of the N channel FET M
5
and the drain of the P channel FET M
8
, and its source is connected to the low level side power source terminal
4
.
The N channel FETs M
4
and M
10
form a second current mirror circuit. The P channel FETs M
7
and M
8
are connected respectively between the drain of the N channel FET M
6
and the high level side power source terminal
5
and between the drain of the N channel FET M
5
and the high level side power source terminal
5
.
The P channel FETs M
7
and M
8
form a current mirror circuit for acting as an active load.
Next, the composition of the driving stage K
2
of the operational amplifier is described.
The driving stage K
2
of the operational amplifier is provided with P channel FETs M
20
, M
21
and M
22
, and N channel FETs for constant current power source M
43
and M
44
.
The N channel FETs for constant current source M
43
and M
44
both have their sources connected to the low level side power source terminal
4
. The N channel FETs for constant current source M
43
and M
44
both are of a current-intake type.
In the P channel FET M
20
, its source is connected to the high level side power source terminal
5
, its gate is connected to the connection point of the drain of the N channel FET M
5
and the drain of the P channel FET M
8
, and its drain is connected to the drain of the N channel FET for constant current power source M
43
. In the P channel FET M
21
, its source is connected to the high level side power source terminal
5
, its gate is connected to the drain of the P channel FET M
20
, and its drain is connected to the gate of the P channel FET M
22
. In the P channel FET M
22
, its source is connected to the high level side power source terminal
5
, its gate is connected to the connection point of the drain of the P channel FET M
20
and the drain of the P channel FET M
21
, and its drain is connected to the drain of the N channel FET for constant current power source M
44
. Next, the composition of the output stage K
3
of the operational amplifier is described.
The output stage K
3
of the operational amplifier is provided with a P channel FET M
23
and an N channel FET M
24
. In the P channel FET M
23
, its source is connected to the high level side power source terminal
5
, its gate is connected to the connection point of the drain of the N channel FET M
5
and the drain of the P channel FET M
8
, and its drain is connected to the output signal terminal
3
. In the N channel FET M
24
, its source is connected to the low level side power source terminal
4
, its gate is connected to the connection point of the drain of the P channel FET M
22
and the drain of the N channel FET for constant current power source M
44
, and its drain is connected to the output signal terminal
3
.
Next, operation of the operational amplifier shown in
FIG. 10
is described. The operational amplifier shown in
FIG. 10
has the input stage K
1
of a wide input range made by connecting in parallel with each other a differential transistor couple composed of the P channel FETs M
1
and M
2
and a differential transistor couple composed of the N channel FETs M
5
and M
6
. The operational amplifier changes the gate voltage of the P channel FET M
23
according to the ratio of signal voltages respectively applied to the signal input terminals
1
and
2
. And a signal passing through the P channel FETs M
20
, M
21
and M
22
changes the gate voltage of the N channel FET M
24
. The potential of the output signal terminal
3
is quickly raised or dropped according to variation quantities of the respective gate voltages of the P channel FET M
23
and the N channel FET M
24
.
First, the case where a voltage applied to the signal input terminal
1
is higher than a voltage applied to the signal input terminal
2
is described. The voltage of the connection point of the drain of the N channel FET M
5
, the drain of the P channel FET M
8
and the drain of the N channel FET M
1
O, namely, the gate voltage of the P channel FETs M
20
and M
23
becomes low. At this time, an electric current which flows from the high level side power source terminal
5
through the P channel FET M
23
to the output signal terminal
3
becomes large. And at this time, the voltage of the connection point of the drain of the P channel FET M
20
and the drain of the N channel FET for constant current power source M
43
, namely, the gate voltage of the P channel FETs M
21
and M
22
becomes high. Hereupon, the voltage of the connection point of the drain of the P channel FET M
22
and the drain of the N channel FET for constant current power source M
44
, namely, the gate voltage of the N channel FET M
24
becomes low.
At this time, an electric current flowing from the output signal terminal
3
through the M channel FET M
24
to the low level side power source terminal
4
becomes very small. That is to say, since an electric current flowing through the N channel FET M
24
is in a shutoff state, an electric current flowing from the high level side power source terminal
5
through the P channel FET M
23
can quickly raise the potential of the output signal terminal
3
by flowing to the output signal terminal
3
(when charging).
On the other hand, the case where a voltage applied to the signal input terminal
1
is lower than a voltage applied to the signal input terminal
2
is described. The voltage of the connecti

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