Semiconductor memory with floating gate type FET

Details Semiconductor memory with floating gate type FET Semiconductor memory with floating gate type FET

1999-11-10

2001-02-27

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185010, C365S185260

Reexamination Certificate

active

06195292

ABSTRACT:

This application is based on Japanese Patent Application No. HEI 10-322034 filed on Nov. 12, 1998, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor memory based upon a new operation principle. Dynamic random access memories (DRAMs) are known as typical semiconductor memories. One bit data is stored in one memory cell of DRAM which is constituted of one MISFET and one capacitor. DRAMs having ultra fine memory cells and a high capacity are under development. Semiconductor memories capable of realizing a still larger capacity are still desired.
b) Description of the Related Art
A flash memory has drawn attention as semiconductor memories capable of realizing a larger capacity. The flash memory is suitable for realizing a larger capacity because one memory cell is constituted by only one MISFET.
Data is stored in a flash memory by injecting carriers into a floating gate electrode of a floating gate type FET. In order to retain carriers injected into the floating gate electrode, the thickness of an insulating film between the floating gate electrode and the channel region is set to about 8 nm. Carriers are injected via this insulating film into the floating gate electrode by applying a high voltage across the channel region and floating gate electrode. As a high voltage is applied between them, carriers are injected into the floating gate electrode by the Fowler-Nordheim tunneling (FN tunneling) phenomenon.
A voltage of about 10 to 20 V is required in order to inject carriers into the floating gate electrode by the FN tunneling phenomenon. It is therefore difficult to lower the voltage and reduce power consumption.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory capable of realizing a large capacity and a low voltage.
According to one aspect of the present invention, there is provided a semiconductor memory comprising: a semiconductor substrate; a source region and a drain region formed in a surface layer of the semiconductor substrate on both sides of a channel region defined in the surface layer, the source and drain regions being of a first conductivity type; a tunneling insulating film formed on the channel region of the semiconductor substrate, the tunneling insulating film having a thickness which allows carriers to tunnel therethrough by a tunneling phenomenon; a floating gate electrode formed on the tunneling insulating film, the floating gate electrode being disposed so as to overlap neither the source region nor the drain region as viewed along a substrate normal direction; a gate insulating film formed over the channel region and covering the floating gate electrode; and a control gate electrode formed on the gate insulating film, the control gate electrode being disposed so as to become in contact with, or partially overlap, the source and drain regions as viewed along the substrate normal direction, wherein materials of the floating gate electrode and the channel region are selected so that a Fermi level of the floating gate electrode is positioned in an energy band gap of the channel region when an external voltage is not applied between the channel region and the control gate electrode.
As a voltage is applied between the control gate electrode and the source/drain regions, carriers in the channel region are tunneled through the tunnel insulating film and injected into the floating gate electrode. The carriers injected into the floating gate electrode have an energy level near the Fermi level of the floating gate electrode. Since the Fermi level of the floating gate electrode is positioned in the energy band gap of the channel region, the injected electrons cannot enter the channel region by the tunneling phenomenon. Electrons can therefore be retained in the floating gate electrode for a long time.
Since not the FN tunneling phenomenon but the direct tunneling phenomenon is used, data can be written and erased by using relatively low voltages. Since one memory cell is constituted of one floating gate type FET, high integration of memory cells is possible.


REFERENCES:
patent: 5508543 (1996-04-01), Hartstein et al.
patent: 5901084 (1999-05-01), Ohnakado
patent: 5932889 (1999-08-01), Matsumura et al.
patent: 7-302848 (1995-11-01), None
patent: 10-135357 (1998-05-01), None

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