Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-01-21
2001-02-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C257S737000
Reexamination Certificate
active
06190940
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to processes for assembling electronic device components using flip-chip techniques, and more particularly to the assembly of semiconductor IC packages with fine pitch bonding sites.
BACKGROUND OF THE INVENTION
State of the art semiconductor integrated circuit (IC) packages are typically high density interconnection structures in which typically unpackaged IC chips or bare die are connected both mechanically and electrically onto a substrate of silicon, ceramic, or epoxy-glass laminate. The choice of interconnection technique, substrate material, and bonding process steps, all play significant roles in defining the overall assembly technique and its influence on IC package cost and reliability. A variety of interconnection techniques have been used in the microelectronics industry to assemble bare die onto the interconnect substrates. These substrates function as both structural support and as the “fabric” for the electrical interconnections between ICs.
Typically, semiconductor IC packages are assembled using one of a variety of known techniques, e.g. wire bonding, tape automated bonding (TAB), and flip-chip soldering. In general, the design of the IC package depends on the particular capabilities of the manufacturer, the IC package architecture, the relative cost of materials, and the required I/O configuration and density. In turn, the choice of interconnection technique plays a major role in defining the assembly process required for high yield and product reliability.
The most common, and nominally the lowest cost, interconnection technique is wire bonding. However, wire bond connections have the disadvantage of having a large footprint, which results in a large substrate and a necessarily less compact package. As is well known in electronics manufacturing, increased size of any feature in the assembly translates directly into added cost. Moreover, increasing the size of the package increases the length of interconnects, leading to increased lead inductance and resistance, and a degradation in electrical performance. Furthermore, a typical wire bonding apparatus, e.g. a stitch bonder, makes bonds one at a time, a time consuming operation even with advanced high speed bonders currently available.
TAB bonding has the advantages of both a smaller footprint and of partial batch processing. However, TAB assembly generally requires different tooling for each IC design, adding significant cost to this bonding technique. Moreover, TAB assembly is limited to interconnection of perimeter I/O arrays thus limiting the IC design flexibility. Perimeter I/O pads typically have higher pitches and correspondingly lower overall I/O densities than the area I/O arrays that can be used with flip-chip solder bonding. Also TAB bonded interconnections typically show higher capacitance and greater parasitic inductance than flip-chip bonded interconnections.
As has long been recognized, flip-chip bonding provides the best performance at the highest I/O density for either perimeter or area I/O arrays. Furthermore, flip-chip bonding is inherently a batch assembly process which facilitates high speed, high through-put manufacture. Flip-chip packaging is a dominant technology especially in the manufacture of computers and computer peripherals. It is also widely used in the assembly of electronics and photonics packages for communication networks products. The essence of flip-chip assembly is the attachment of semiconductor substrates “upside down” on an interconnection substrate such as a silicon wafer, ceramic substrate, or printed circuit board. The attachment means is typically solder, in the form of balls, pads, or bumps (generically referred to hereinafter as bumps). The solder bumps may be applied to the semiconductor chip, or to the interconnection substrate, or to both. The chip is placed in contact with the substrate and the solder is heated to reflow the solder and attach the chip to the substrate. The solder bonds form pillars or beams that offset the joined surfaces with respect to one another leaving a gap therebetween. After the chip is bonded to an interconnection substrate the resulting assembly typically undergoes further thermal cycling during additional assembly operations. The final product also is exposed to wide temperature changes in the service environment. The chip package is typically a semiconductor, and the interconnection substrate may be epoxy, ceramic, or an epoxy-glass laminate. The material of the chip, and the material of the interconnection substrate, have thermal expansion coefficients that are different from one another. The differential expansion that the assembly invariably undergoes results in stresses on the solder bonds which can cause stress cracking and ultimately failure of the electrical path through the solder bond. To avoid solder bond failures due to mechanical stress, the gap between the surfaces joined by the bond is typically filled with an underfill material. The underfill provides additional mechanical strength for the assembly and also protects the gap from moisture and other corrosive contamination. Underfill materials are adhesive and water insoluble. They are typically epoxy materials.
The underfill is applied after completion of the solder bonding operation. The underfill material is typically a polymer and is applied as a prepolymer liquid. Consequently, the viscosity of the underfill material as it is dispensed into the gap should be relatively low. The liquid prepolymer flows freely into the gap and, due to the relatively small gap in state of the art packages, flow is aided substantially by surface tension, and the liquid prepolymer is “wicked” into the gap. However, in some cases entrapped air, or incomplete wetting of the surfaces of the space being filled, inhibits flow or prevents wicking, causing voids in the underfill. A technique for overcoming this problem is described in patent application Ser. No. 08/956,527, filed Oct. 23, 1997, and assigned to the same assignee as this application. The technique described and claimed in the prior application involves coating one or both of the elements being bonded with epoxy and thermocompression bonding them together so that the solder bumps penetrate the epoxy layer. The epoxy is cured as the bump bonds are effected. In this way complete coating of the surfaces being bonded, and complete filling of the gap therebetween, is assured.
For a variety of reasons, flip-chip assembly is usually considered to be the most expensive of the known assembly techniques. This is especially true for “high performance” IC package designs which often use multi-layer co-fired ceramics (MCM-C) or deposited thin film ceramic or silicon substrates (MCM-D) as the interconnection substrate. The less expensive alternative is a typical printed wiring board, i.e epoxy-glass fiber laminate. However, as the I/O count and density increases in epoxy-glass fiber laminates, the solder bumps typically used for interconnection are too closely spaced and frequently bridge together. This is partly due to the fact that the formation of solder bumps relies on surface tension to create ball shaped solder bodies at the interconnection site. Lateral flow of solder during this process is unconstrained, and lateral flow sometimes exceeds the desired boundaries leading to bridging to the adjacent ball or pad.
The foregoing problems are especially severe in microbumped packages, in which the bump height is so small that the small gap resulting after the bonding operation cannot be filled consistently by relying only on fluid dynamics, and voids are frequent. The bump bond pitch in these packages is also very small, resulting in solder bumps melting together and shorting.
STATEMENT OF THE INVENTION
We have developed an underfill technique for solder bonded assemblies that does not rely on wicking or fluid flow for filling the gap between the solder bonded surfaces. According to this technique a layer of epoxy underfill material is applied to one or both surfaces prior to solder bonding, and t
DeFelice Richard Alden
Dittmann Eric William
Sullivan Paul A.
Lucent Technologies - Inc.
Nelms David
Thomas Kayden Horstemeyer & Risley LLP
Vu David
Wilde Peter V. D.
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