I.C. carrier insert

Special receptacle or package – Holder for a removable electrical component – Including electrical field – magnetic field – or static...

Reexamination Certificate

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Details

C206S724000, C439S330000

Reexamination Certificate

active

06182829

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to Integrated Circuit (IC) chip carriers for transport and handling of IC devices, and more specifically to a generic insert for chip carriers which allows universality across device types and applications.
2. Description of the Prior Art
In the manufacture of electronic devices such as Integrated Circuits (IC's), there is constant pressure to produce less expensive, dimensionally smaller devices while simultaneously increasing the density of electronic functions within the devices. In order to reduce the unit costs in the production of such devices, manufacturers have increased the test speed of the devices by testing a plurality of the devices at the same time.
It has become standard practice within the semiconductor industry to place a number of electronic devices to be tested on a test tray and position them so as to be engaged by a test head plate having a number of corresponding test contactors. Each device is placed on a seat of a device called a chip carrier, further described below. A number of chip carriers are then positioned in both columns and rows on a test tray. The test tray having a number of chip carriers is arranged so as to be in vertical alignment (either above or below) with a test fixture. The test fixture includes test contactors (test pins) for contact with pins of each device to be tested for supplying and receiving the test signals from the device. Each carrier module is aligned with a corresponding test contactor so that when either the test tray or the test fixture are moved in a vertical direction toward the other, the contactor engages the electronic device positioned within the carrier module.
The contactor is provided with a number of test pins or leads which come into electrical communication with the leads of the electronic devices to be tested. The automatic test handler is electrically connected to a electronic device test system, for example, an IC tester which includes a test signal generator for supplying a test signal to the device, and with a signal comparator for analyzing the results of the test. Based on such results, the electronic devices are transferred to another location in the test process and sorted for proper handling.
The size and configuration of standard electronic chips are rapidly changing. Some of the high speed ICs have very short signal leads, instead of the relatively longer leads used in the conventional package types, such as QFP (quad-flat-pack). For example, newer types of IC devices are molded in packages called thin-quad-flat-pack (TQFP). When utilizing a test tray to test such IC devices, it is necessary to employ a new carrier module to secure an electrical isolation between the leads and also to eliminate the deformation of the leads of the IC devices.
IC carriers have typically been rather complex three dimensional devices fabricated by a variety of means, typically from some thermal-setting or thermoplastic material. Due to the complex three dimensional fine-structure sometimes required in the carriers due to the material nature of the carriers, brittleness and/or fragileness of the carrier may ensue. Also, as mentioned above, minor modifications in the IC device package or the environment of the application may cause a redesign and retool of the carrier, which is often an expensive proposition.
SUMMARY OF THE INVENTION
The present invention overcomes many of the disadvantages associated with the prior art by providing an insert for use within integrated circuit (IC) chip carriers to provide universality across device types and applications at a low design and fabrication cost.
In a preferred embodiment, the present invention may function as a generic carrier floor and/or adaptor insert which will allow both quad-flat-pack (QFP) and thin-quad-flat-pack (TQFP) ICs to be placed within a variety of existing carriers. In another embodiment, the present invention may function as a generic carrier floor and/or adaptor insert which will allow both quad-flat-pack (QFP) and thin-quad-flat-pack (TQFP) ICs to utilize a single IC carrier, a feature which currently prevailing embodiments would require two unique IC carriers. In a preferred embodiment, the IC insert is fabricated from a metal (such as stainless steel), which in addition to its characteristic malleability, also offers the attributes of strength and a relatively low cost. In alternate embodiments, the IC insert may be fabricated from other materials, such as plastic, polyimide, etc.
In a preferred embodiment, the insert of the present invention is formed from a two-dimensional metal (such as stainless steel) blank which contains protruding tabs and isolation windows defined within the blank which provide access to the leads of the associated IC device. The isolation windows also provide DC isolation between the leads of the IC and the IC insert itself. The protruding tabs of the two dimensional metal blank may be bent so as to define a third dimensional aspect to the embodiment which may serve to secure the IC insert to the chip carrier. In alternate embodiments, the insert may be secured to the carrier via glue, screws, rivets, etc.


REFERENCES:
patent: 1740424 (1929-12-01), Blaine
patent: 1910888 (1933-05-01), Gerald
patent: 4450955 (1984-05-01), Featherston
patent: 4681221 (1987-07-01), Chickanosky et al.
patent: 4706161 (1987-11-01), Buckingham
patent: 4725918 (1988-02-01), Bakker
patent: 4832612 (1989-05-01), Grabbe et al.
patent: 4848571 (1989-07-01), Fullar
patent: 5167326 (1992-12-01), Murphy

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