Method of making dishing-free insulator in trench isolation

Details Method of making dishing-free insulator in trench isolation Method of making dishing-free insulator in trench isolation

2000-10-13

2001-11-13

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S430000, C438S435000, C438S437000

Reexamination Certificate

active

06316331

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of making a trench isolation in a semiconductor substrate, and more particularly to a method of making dishing-free insulator in trench isolation.
BACKGROUND OF THE INVENTION
Conventional method to form STI (Shallow Trench Isolation) structure is shown in
FIGS. 1A
,
1
B, and
1
C. In
FIG. 1A
, a pad oxide layer
11
and a silicon nitride layer
12
are sequentially formed on a substrate
10
. Next, a photoresist layer
14
with a trench pattern is formed on the silicon nitride layer
12
by a photolithography process. Then a trench
16
is formed by performing an anisotropic etching on the substrate
10
according to the trench pattern on the photoresist layer
14
.
In
FIG. 1B
, after removing the photoresist layer
14
, a thermal oxide layer
18
is formed on the trench surface by thermal oxidation at
20
a temperature of about 900° C.~1100° C. An oxide layer
20
is formed over the substrate
10
by atmospheric chemical vapor deposition (APCVD) with a reaction gas of tetra-ethyl-ortho-silicate (TEOS).
In
FIG. 1C
, a chemical mechanical polishing (CMP) process is performed to polish the TEOS oxide layer
20
above the silicon nitride
12
. The remained TEOS oxide layer filled in the trench
16
is called an oxide plug
20
a
and is used for isolation. However, the CMP process will cause a dishing-type surface to be formed on the surface of the oxide plug
20
a
when the trench is wide, as shown in the figure.
In U.S. Pat. No. 6,110,800 Chou disclosed a method to form a shallow trench isolation (STI) structure. FIGS.
2
A~
2
G show schematically the Chou's process in forming a STI structure by repeated formations of silicon sidewall spacers and thermal oxidation of the silicon sidewall spacers.
In
FIG. 2A
, a photoresist
202
is formed over a semiconductor substrate
200
. A photolithography process is performed to transfer a pattern onto the substrate
200
. Then an anisotropic etching is performed to form a trench
204
and a trench
206
on the substrate. The trench
204
is wider than the trench
206
.
In
FIG. 2B
, an ion implantation is performed to form a channel stop
205
under the trench
204
,
206
, and then the photoresist layer
202
is removed. A pad oxide layer
208
and a silicon nitride
210
are sequentially formed over the substrate
200
.
In
FIG. 2C
, a polysilicon layer is deposited over the substrate
200
through LPCVD and performing an etching back process to form a sidewall spacer
212
b
and a sidewall spacer
212
a
respectively on each side of the trench
204
and the trench
206
over the silicon nitride layer
210
.
In
FIG. 2D
, an oxidation process is performed to oxidize the sidewall spacers
212
a
,
212
b
. Since the trench
206
is narrow, an oxide plug
214
a
is formed to fill the trench
206
. The trench
204
is wide, an oxide sidewall aspacer
214
b
may be formed without filling the trench
204
. In order to fully fill the trench
204
with oxide, another polysilicon sidewall spacer
216
is repeatedly formed and oxidized until an oxide plug
218
is formed to fully fill the trench
204
as shown in FIG.
2
E.
In
FIG. 2F
, an oxide layer
220
is formed over the substrate
200
to have a better planar surface.
In
FIG. 2G
, an anisotropic etching process is performed to remove the oxide layer
220
, the silicon nitride layer
210
, and the pad oxide layer
208
outside the trenches
204
,
206
to expose the substrate
200
.
The Chou's method needs repeated formations of silicon sidewall spacers and thermal oxidation of the silicon sidewall spacers. Though this process can somewhat eliminate the dishing-effect in a wider trench, it is too complicated and costly.
OBJECT OF THE INVENTION
It is therefore an object of the present invention to provide a method to form a dishing-free insulator in trench isolation without repeated formations of silicon sidewall spacers and thermal oxidation of the silicon sidewall spacers.


REFERENCES:
patent: 4471525 (1984-09-01), Sasaki
patent: 4847214 (1989-07-01), Robb et al.
patent: 5926717 (1999-07-01), Michael et al.
patent: 6110800 (2000-08-01), Chou
patent: 6136664 (2000-10-01), Economikos et al.

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