Memory device with command buffer

Details Memory device with command buffer Memory device with command buffer

1998-08-28

2001-02-20

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230010, C365S230030, C365S236000, C365S189011, C365S189040

Reexamination Certificate

active

06192002

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to memory devices, and more particularly, to a memory device having the ability to perform block writes in a bursting fashion.
2. Description of the Related Art
Memory devices, such as synchronous graphics random access memories (SGRAM) and synchronous dynamic access memories (SDRAM), have been widely used to enhance the performance of computer systems executing memory intensive applications. SGRAM devices are especially adapted to improving graphics performance, and SDRAM devices fill a more general purposes memory role.
SCRAM devices have been equipped with features tailored to enhance the processing of repetitive tasks that are commonly seen in graphics applications. One such feature used in specialized graphics memories is a block write. During a block write, multiple cells in the graphics memory are simultaneously written with the same value. For example, eight cells may be accessed concurrently. Because of the multiplicity of cells being written, a block write takes more time to complete than a normal single cell write access. Typically, a block write is completed in two clock cycles, as opposed to one clock cycle for a normal write.
In a normal write access, the digit lines associated with the accessed cell are equilibrated prior to the next clock cycle in response to an equilibrate pulse. Subsequent accesses are typically performed in a bursting fashion, where internal counters for incrementing the column or row being accessed within the memory device are toggled every cycle. Because the counters are incremented during the block write, they no longer point to the desired next column or row.
Both of these situations pose problems for a block write that takes multiple cycles to complete. If an equilibrate pulse is received during a block write, the data being written would be compromised. Accordingly, specialized logic is used to inhibit the equilibrate pulse for any clock cycles occurring during the block write. To address the counter synchronization issue, a storage device (e.g., register) is used to store the column counter and restore the counter to the proper value after completion of the block write. Both of these solutions increase the complexity and size of the graphics memory, thus increasing its cost. Due to the clock synchronization problem inherent in the block write, bursting of block writes is not achievable. General purpose memory devices, such as SDRAM devices, are not typically equipped with block write functionality.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a memory device including a memory array, an external clock terminal, and control logic. The memory array is arranged in rows and columns. The external clock terminal is adapted to receive an external clock signal. The external clock signal has at least a first cycle and a second cycle. The first cycle includes a first edge and the second cycle includes a second edge. The control logic is coupled to the memory array and the external clock terminal and adapted to write to a first plurality of the columns in a specified row during the first and second cycles. The control logic is further adapted to suspend the external clock signal to suppress the second edge of the second cycle while writing to the first plurality of the columns.
Another aspect of the present invention is seen in a method for accessing a memory device arranged in rows and columns. The method includes receiving an external clock signal. The external clock signal has at least a first cycle and a second cycle. The first cycle includes a first edge and the second cycle includes a second edge. A first plurality of columns in a specified row are written to during the first and second cycles. The external clock signal is suspended to suppress the second edge of the second cycle while writing to the first plurality of the columns.


REFERENCES:
patent: 5655105 (1997-08-01), McLaury
patent: 5657287 (1997-08-01), McLaury et al.
patent: 5813023 (1998-09-01), McLaury
patent: 5901111 (1999-05-01), McLaury et al.
patent: 6006290 (1999-12-01), Suh
patent: 6026496 (2000-02-01), Wright et al.
patent: 6097781 (2000-08-01), Wright et al.

Affiliated with

Also associated with

Rating

Memory device with command buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device with command buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device with command buffer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2611587