Active solid-state devices (e.g. – transistors – solid-state diode – Specified wide band gap semiconductor material other than... – Diamond or silicon carbide
Reexamination Certificate
2000-01-19
2001-10-16
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Specified wide band gap semiconductor material other than...
Diamond or silicon carbide
C257S279000, C257S281000
Reexamination Certificate
active
06303947
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to field-effect transistors (hereinafter referred to as FET), in particular, junction-type FET (hereinafter referred to as JFET) and metal-semiconductor junction type FET (hereinafter referred to as MESFET), which use silicon carbide as a semiconductor material and are highly expected to be used as power semiconductor devices, and also relates to a method for manufacturing such field-effect transistors.
BACKGROUND OF THE INVENTION
Silicon carbide (that will be referred to as SiC) has a wide band gap, and its maximum breakdown electric field is larger than that of silicon by one order of magnitude. Thus, SiC has been highly expected to be used as a material for power semiconductor devices in the next generation. Up to the present, various types of electron devices, in particular, those for switching large power at high temperatures, have been developed, using single-crystal wafers, such as 4H—SiC and 6H—SiC. These crystals are alpha-phase SiC in which a zinc-blend structure and a wurtzite structure are superposed on each other. Also, semiconductor devices have been fabricated using crystals of beta-phase SiC, such as 3C—SiC.
Recently, power devices, such as Schottky diodes, vertical MOSFET and thyristors, and CMOS-IC as the most popular semiconductor devices, have been fabricated using SiC as a semiconductor material, and it has been confirmed that these devices exhibit far better characteristics than conventional Si semiconductor devices.
FIG. 9
is a cross-sectional view showing one example of power JFET that has been reported. In the JFET of
FIG. 9
, an n drift layer
11
b
is laminated on an n
+
drain layer
11
a
, and a p
+
embedded region
12
is formed in the n drift layer
11
b
by implanting ions at a high accelerating-field voltage. An n channel region
20
is formed by introducing n-type impurities into the n drift layer
11
b
located above the p
+
embedded region
12
, and p gate region
14
and n
+
source region
13
are formed in a surface layer of the n channel region
20
. A source electrode
17
is formed in contact with the n
+
source region
13
, and a drain electrode
18
is formed in contact with the n
+
drain layer
11
a
, while a gate electrode
16
is formed in contact with the p gate region
14
. A gate insulating film
15
is formed on the surface of the n channel region
20
interposed between two n
+
source regions
13
, and cooperates with the gate electrode
16
to provide a MOS gate. The source electrode
17
is in contact with not only the n
+
source region
13
but also a p
+
contact region
12
a
that is in contact with the p
+
embedded region
12
.
The n channel region
20
is interposed between the p
+
embedded region
12
and the p gate region
14
. When a positive voltage is applied to the gate electrode
16
, an accumulation layer in which carriers are accumulated is induced in a portion of the n channel region
20
located below the gate insulating film
15
, thus allowing current to flow from the drain electrode
18
to the source electrode
17
. When a negative voltage is applied to the gate electrode
16
, a depletion layer spreads out from the p gate region
14
into the n channel region
20
, thereby to narrow a conduction region of the n channel region
20
, and thus control current flow between the source electrode
17
and the drain electrode
18
. Thus, the JFET of
FIG. 9
is capable of switching current between the source and the drain, with a positive or negative voltage applied to the gate electrode
16
.
While the JFET having the structure of
FIG. 9
exhibits mostly favorable characteristics, it still needs to be improved in the following two aspects.
Firstly, there is always a demand for an increase in the gain with respect to gate voltage. Secondly, if the potential of the p gate region
14
becomes lower than that of the p
+
embedded region
12
, holes or current flow from the p
+
embedded region
12
into the p gate region
14
. As a result, the device tends to be turned on by mistake.
In the JFET of
FIG. 9
, the impurity concentration is controlled by, for example, implanting ions over the entire area of the n channel region
20
, for the purpose of controlling switching characteristics. In this case, however, the n channel region
20
may affect spreading of a depletion layer between the p gate region
14
and the n drift layer
12
, thus limiting control of the breakdown voltage.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a silicon carbide vertical FET which provides a high breakdown voltage and a large gain with respect to gate voltage, and which operates with high stability.
To accomplish the above object, the present invention provides a silicon carbide vertical FET which comprises a first conductivity type silicon carbide drain layer; a first conductivity type drift layer comprising silicon carbide, which is laminated on the first conductivity type silicon carbide drain layer; a second conductivity type gate region and a first conductivity type source region that are formed in selected portions of a surface layer of the first conductivity type drift layer, such that the gate region and the source region are spaced from each other; a second conductivity type embedded region formed in a selected portion of the first conductivity type drift layer below the second conductivity type gate region and the first conductivity type source region, such that the embedded region is not connected to the gate region and the source region; a gate electrode formed in contact with a surface of the second conductivity type gate region; a source electrode formed in contact with a surface of the first conductivity type source region; and a drain electrode formed on a rear surface of the first conductivity type drain layer, wherein the second conductivity type embedded region has the same potential as the gate electrode.
More specifically, a second conductivity type contact region may be formed which extends from the surface of the first conductivity type drift layer to reach the second conductivity type embedded region, and a contact electrode that contacts with the surface of the second conductivity type contact region may be connected to the gate electrode. Alternatively, a recess may be formed in the first conductivity type drift layer such that the recess extends from the surface of the first conductivity type drift layer to reach the second conductivity type embedded region, and an embedded electrode received in the recess for contact with an exposed surface of the second conductivity type embedded region may be connected to the gate electrode.
In the silicon carbide vertical FET fabricated by the above-described methods, depletion layers spread out from both the second conductivity type embedded region and second conductivity type gate region into the first conductivity type drift layer located above the second conductivity type embedded region, resulting in a significantly improved gain with respect to gate voltage. Since the second conductivity type embedded region and the second conductivity type gate region have the same potential, no parasitic transistor appears between the embedded region and the gate region, and no current flows between these regions. Thus, the present FET is free from faulty operations due to current that would otherwise flow between the embedded region and the gate region.
In the silicon carbide vertical FET, the second conductivity type gate region may be formed in a surface layer of the first conductivity type drift layer that is located above a portion where the second conductivity type embedded region is not formed. In another form of the invention, the gate electrode is formed on a gate insulating film over a surface layer of the first conductivity type drift layer that is located above a portion where the second conductivity type embedded region is not formed. In a further form of the invention, a metal film that forms a
Chaudhuri Olik
Fuji Electric & Co., Ltd.
Ha Nathan W.
Rossi & Associates
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