Semiconductor memory

Details Semiconductor memory Semiconductor memory

2000-02-10

2001-02-13

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185230, C365S203000

Reexamination Certificate

active

06188612

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory. Specifically, the present invention relates to a semiconductor read only memory wherein information stored in memory cells are read.
2. Description of the Related Art
FIG. 5
shows a conventional semiconductor read only memory (ROM)
500
. The semiconductor read only memory
500
includes a memory cell array including a plurality of memory cell transistors M
1
, M
2
, M
3
, . . . Mn, word lines WL
1
, WL
2
, . . . WLn, bit lines BIT
11
, BIT
12
, . . . BIT
1
n
, and bit lines BIT
21
, BIT
22
, . . . BIT
2
n
. (The memory cell transistor Mn and the bit lines BIT
1
n
and BIT
2
n
are not shown.) The plurality of memory cell transistors M
1
, M
2
, M
3
, . . . Mn are arranged in a matrix, and these transistors are MOS transistors. The word lines WL
1
, WL
2
, . . . WLn are connected to gate electrodes of the plurality of memory cell transistors. The bit lines BIT
11
to BIT
1
n
are connected to drain electrodes of the plurality of memory cell transistors, and the bit lines BIT
21
to BIT
2
n
are connected to source electrodes of the plurality of memory cell transistors.
The bit lines BIT
11
and BIT
12
are also connected to source electrodes of bit line selecting transistors Tr
12
and Tr
11
, respectively. The bit lines BIT
21
and BIT
22
are also connected to drain electrodes of bit line selecting transistors Tr
21
and Tr
22
, respectively. Gate electrodes of the bit line selecting transistors Tr
11
and Tr
12
are connected to bit line selecting lines BS
11
and BS
12
, respectively. Drain electrodes of the bit line selecting transistors Tr
11
and Tr
12
are connected to a drain electrode of a charging transistor Tr
4
for a reading operation (hereinafter, referred to as “read charging transistor Tr
4
”). A source electrode and a gate electrode of the read charging transistor Tr
4
are connected to a power supply VDD. Gate electrodes of the bit line selecting transistors Tr
21
and Tr
22
are connected to bit line selecting lines BS
21
and BS
22
, respectively. Source electrodes of the bit line selecting transistors Tr
21
and Tr
22
are connected to a ground GND.
Now, an operation for reading data stored in the memory cell transistor M
2
of the semiconductor read only memory
500
is described.
Consider a case where data stored in the memory cell transistor M
2
is “0”. In order to read the data stored in the memory cell transistor M
2
, the bit lines BIT
12
and BIT
21
connected to the memory cell transistor M
2
conduct a current. At this time, the bit line selecting lines BS
11
and BS
21
are high, whereas the bit line selecting lines BS
12
to BS
1
n
and BS
22
to BS
2
n
, except the bit line selecting lines BS
11
and BS
21
, are low.
The selected bit line BIT
12
is charged up to an intermediate potential through the read charging transistor Tr
4
by the power supply VDD, whereas the selected bit line BIT
21
goes to a ground level. Then, the word line WL
2
connected to the memory cell transistor M
2
goes high. The word line WL
1
and the word lines WL
3
to WLn, except the word line WL
2
, remain low. The selected bit lines BIT
12
and BIT
21
are connected to each other through the memory cell transistor M
2
, thereby forming a DC current route from the power supply VDD to the ground GND. The potential of the power supply VDD is resistive-divided by each of the resistances which are loads of the DC current route, resulting in the potential of an output signal line Dbit.
Next, consider a case where the data stored in the memory cell transistor M
2
is “1”. In this case, even if the word line WL
2
goes high, the memory cell transistor M
2
does not conduct a current. Therefore, the DC current route is not formed, and the output signal line Dbit is maintained at the intermediate potential. A sense amplifier (not shown) is capable of reading data stored in a memory cell from the change of level of the output signal line Dbit caused by the difference in data between memory cell transistors.
In the semiconductor read only memory
500
shown in
FIG. 5
, a sense amplifier senses a voltage drop which has been caused by a current flowing in a memory cell transistor selected by a bit line and a word line. In
FIG. 5
, a transition of the word line WL
2
to a high level selects the memory cell transistor M
2
. At this time, the memory cell transistors M
1
and M
3
adjacent to the memory cell transistor M
2
are also selected. Therefore, the bit line BIT
21
connected to the memory cell transistor M
1
is connected to the bit line BIT
11
through the memory cell transistor M
1
. Since the bit line BIT
11
contains a charge remaining from the previous read operation, a current flows to the bit line BIT
21
through the memory cell transistor M
1
. This varies the value of the currents flowing through the bit lines BIT
21
and BIT
12
.
Thus, the semiconductor read only memory
500
has difficulty in correctly reading data stored in a memory cell transistor.
Furthermore, since the semiconductor read only memory
500
is required to keep currents flowing through bit lines during a reading operation, the power consumption is increased. In order to address such a problem, for example, Japanese Laid-Open Publication No. 9-231783 discloses a method for correctly reading data by measuring the potential of a bit line which is less susceptible to a leakage current.
FIG. 6
shows an NOR type semiconductor storage device
600
wherein the potential of a bit line which is less susceptible to a leakage current is measured.
In the NOR type semiconductor storage device
600
, a plurality of memory cells are connected to a word line WLn. Therefore, when a word line WL
2
goes high, memory cell transistors M
1
, M
2
, and M
3
connected to the word line WL
2
are turned ON. As a result, a bit line current Ibit
1
is divided into, for example, three currents routed through route
1
, route
2
and route
3
.
When leakage currents flowing through route
2
and route
3
occur, the value of bit line current Ibit
1
varies. However, since the resistance between the source electrode and the drain electrode of the memory cell transistors M
2
is larger relative to the off resistances of the bit line selecting transistors Tr
11
and Tr
12
, a variation of a bit line current Ibit
2
flowing through a bit line BIT
21
is smaller than a variation of a bit line current Ibit
1
flowing through a bit line BIT
12
.
In the semiconductor read only memory
500
shown in
FIG. 5
, the potential of the output signal line Dbit is affected by the variation of the bit line current Ibit
1
. Accordingly, it is difficult to correctly read information stored in the memory cell transistors. In the NOR type semiconductor read only memory
600
shown in
FIG. 6
, information stored in the memory cell transistors are read by using the bit line current Ibit
2
flowing through the bit line BIT
21
, whose variation is less than that of the bit line current Ibit
1
flowing through the bit line BIT
12
. Specifically, the information stored in the memory cell transistors can be read correctly from the potential of the output signal line Dbit which is caused by a leakage section connected to the bit line BIT
21
through a column selecting section. However, since the bit line current is kept flowing through the leakage section, the power consumption is large.
Furthermore, in the NOR type semiconductor read only memory
600
shown in
FIG. 6
, the resistance of the leakage section is set to a large value in order to improve the accuracy of a reading operation. Such a large resistance value of the leakage section increases a change of the potential of a bit line to be read, thereby improving the accuracy of a reading operation. However, as the resistance value increases, the reading rate decreases accordingly.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a semiconductor memory includes: a plurality of memory cell transistors; a plurality of first bit lines; a plurality of second bit l

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