Output buffer circuit for semiconductor device

Details Output buffer circuit for semiconductor device Output buffer circuit for semiconductor device

1998-10-06

2001-02-27

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S538000, C326S083000

Reexamination Certificate

active

06194922

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output buffer circuit for a semiconductor device, and in particular to an output buffer circuit capable of improving an output speed.
2. Description of the Conventional Art
FIG. 1
is a block diagram of a conventional output buffer circuit including an output control circuit
10
, and inverters
11
,
12
, each of which is composed of a plurality of NMOS transistors.
The operation of the conventional output buffer circuit will now be described.
When the inverters
11
,
12
respectively receive clock signals NU
1
, NU
2
of a high level and clock signals ND
1
, ND
2
of a low level, which are outputted from the output control circuit
10
, the inverters
11
,
12
output data signals at a high level, and when the inverters
11
,
12
respectively receive clock signals NU
1
, NU
2
at a low level and clock signals ND
1
, ND
2
at a high level, the inverters
11
,
12
output data signals at a low level.
Here, the clock signals NU
1
, NU
2
for outputting the data signals at the high level have different roles from each other.
That is, the clock signal NU
1
is applied to obtaining prompt data output, and the clock signal NU
2
, a delayed signal compared with the clock signal NU
1
, serves as a signal which maintains output of a data signal at a high level, and improves the output speed by reducing the instantaneous peak current I
PC
, which is generated when the output is at a high level, as shown in
FIG. 2
, and therefore for reducing noise due to the peak current I
PC
.
The conventional output buffer circuit maintains the high level data output which is the high level at a VCC-Vth level by employing pull-up NMOS transistors NM
1
, NM
2
, thereby reducing the amount by which the data out is charged at the high level and reducing the noise generated when the data output is transited from the high level to the low level.
However, in the conventional output buffer circuit, the output level is limited to the VCC-Vth level due to using the NMOS transistors. Therefore, when the VCC level is increased by &Dgr;v, the output level is also increased by &Dgr;V. In result, the output level is increased in accordance with an increase in VCC, thus increasing the noise and therefore slowing down the output speed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a video signal processing apparatus that substantially obviates at least one of problems or disadvantages of the conventional art.
Another object of the present invention is to provide an output buffer circuit which is capable of uniformly maintaining an output level regardless of a variable VCC level and of improving an output speed.
An object of the present invention is to provide a constant voltage generation circuit which outputs a constant voltage at a constant level with respect to a variable VCC.
To achieve the above objects, there is provided an output buffer circuit which includes a constant voltage generation circuit receiving a variable VCC supply voltage and generating a constant voltage at a predetermined level, an inverter outputting data signals in accordance With the constant voltage outputted from the constant voltage generation circuit and first and second clock signals, a clock signal generation unit generating a third clock signal having a predetermined interval in accordance with the first clock signal and the data signals outputted from the inverter, and a pull-up transistor pulling up the output data signals of a high level at a predetermined level in accordance with the third clock signal.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 5138201 (1992-08-01), Ohbayashi et al.
patent: 5495195 (1996-02-01), Fontana et al.
patent: 5831465 (1998-11-01), Watarai
patent: 5898315 (1999-04-01), Knaack

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