Overload recovery circuit and method

Details Overload recovery circuit and method Overload recovery circuit and method

2001-01-18

2001-11-13

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S267000

Reexamination Certificate

active

06317000

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to high-speed CMOS operational amplifiers, and also to circuitry that reduces the amount of delay required for a high-speed CMOS operational amplifier to recover from a saturation condition.
U.S. Pat. Nos. 5,546,045, 4,622,521 and 4,714,896 represent the closest known prior art. U.S. Pat. No. 5,546,045 discloses a rail-to-rail bipolar class AB output stage.
It should be appreciated that until now, there have been very few commercially available high-speed CMOS operational amplifiers. This is because until very recently CMOS transistors that could be readily manufactured using reasonably low-cost CMOS integrated circuit manufacturing processes have had minimum channel length values that are not short enough (i.e., not less than about 0.7 microns) to allow CMOS operational amplifiers manufactured with such CMOS integrated circuit manufacturing processes to compete effectively with high-speed bipolar operational amplifiers manufactured using standard bipolar integrated circuit manufacturing processes. This is because the longer minimum channel lengths of the prior CMOS manufacturing processes result in large gate capacitances of all of the transistors, especially the pull-up transistors and pull-down transistors of the amplifier output stages. The large gate capacitances result in reduced circuit operating speeds compared to what has been achievable using of conventional bipolar integrated circuit manufacturing processes. It is possible for operational amplifiers made with a typical CMOS manufacturing process to have operating speeds comparable to those of conventional bipolar integrated circuit operational amplifiers only if the minimum channel lengths for transistors made using that CMOS manufacturing process are sufficiently small (e.g., less than approximately 0.6 microns for a circuit designed for use with low power supply voltages, or as much as approximately 2.0 microns for a circuit designed for use with high power supply voltages).
In prior art CMOS operational amplifiers, if the output voltage responds to the input signal by increasing to a level close to the positive supply voltage, the input stage of the operational amplifier, which typically includes a differential input stage and a folded cascode stage connected to the gate of the P-channel pull-up transistor, causes the gate of the P-channel pull-up transistor to be pulled down to a level near the ground or negative supply voltage level in order to adequately turn on the P-channel pull-up transistor. Typically, there is a large capacitance coupled to the conductor connected to the gate of the P-channel pull-up transistor. The large capacitance typically includes the gate capacitance of the pull-up transistor and the capacitance of the compensation capacitor of the operational amplifier. Consequently, if the input signal applied to the operational amplifier is rapidly decreased, the input stage of the operational amplifier needs to charge the gate voltage of the P-channel pull-up transistor to a high voltage nearly equal to the positive supply voltage before the P-channel pull-up transistor is turned off. The current supplied by the input stage of the operational amplifier to accomplish the charging up of the large capacitance coupled to and associated with the gate of the P-channel pull-up transistor is small, typically about 100 microamperes. Consequently, there is a substantial delay, referred to herein as an overload recovery delay, before the operational amplifier output voltage responds to the change in the input signal. The foregoing problem for the P-channel pull-up transistor is accompanied by an analogous overload recovery delay problem for the N-channel pull down transistor. The above described overload recovery delay problems have made CMOS operational amplifiers unsuitable for certain applications.
The above described problems for CMOS operational amplifiers also apply directly to CMOS comparators.
For a long time there has been a need for an inexpensive, high-speed integrated circuit operational amplifier with rapid recovery from a saturation or overload condition. This need has not been satisfied by prior CMOS operational amplifiers. Similarly, the need for an inexpensive, high-speed integrated circuit comparator with rapid recovery from a saturation or overload condition is not been satisfied by prior CMOS comparators.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide an inexpensive high-speed CMOS amplifier having rapid recovery from a saturation or overload condition.
It is another object of the invention to provide an inexpensive high-speed CMOS differential amplifier having rapid recovery from a saturation or overload condition.
It is another object of the invention to provide an inexpensive high-speed CMOS comparator having rapid recovery from a saturation or overload condition.
It is another object of the invention to provide an inexpensive high-speed CMOS differential amplifier which limits current supplied to a portion of the amplifier circuit, for example, a portion of a slew boost circuit in the amplifier circuit, during the same conditions wherein an output transistor of the differential amplifier is saturated.
It is another object of the invention to provide an inexpensive, high-speed integrated circuit CMOS operational amplifier which competes effectively in the marketplace with bipolar integrated circuit operational amplifiers.
It is another object of the invention to provide an inexpensive, high-speed integrated circuit CMOS comparator which competes effectively in the marketplace with bipolar integrated circuit comparators.
Briefly described, and in accordance with one embodiment thereof, the invention provides an operational amplifier including an input stage (
13
) receiving an input signal (Vin) and having first (
14
) and second (
16
) output terminals, and also including an output stage (
10
) having a pull-up transistor (M
11
) and a pull-down transistor M
2
. The pull-up transistor has a source coupled to a first supply voltage (V
DD
), a gate coupled to the first output terminal (
14
), and a drain coupled to an output conductor (
22
) conducting an output signal (Vout). The pull-down transistor (M
2
) has a source coupled to a second supply voltage (V
SS
), a gate coupled to the second output terminal (
16
), and a drain coupled to the output conductor (
22
). An AB control circuit (
20
) is coupled between the gates of the pull-up transistor and a pull-down transistor. A first overload recovery circuit (X) is coupled between the output conductor (
22
) and the gate of the pull-up transistor for limiting the voltage on the gate of the pull-up transistor in response to the output voltage (Vout) when the output voltage is within a first predetermined range of the first supply voltage (V
DD
). A second overload recovery circuit (Y) is coupled between the output conductor (
22
) and the gate of the pull-down transistor for limiting the voltage on the gate of the pull-down transistor in response to the output voltage (Vout) when the output voltage is within a second predetermined range of the second supply voltage (V
SS
).


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