Pulse density modulator

Details Pulse density modulator Pulse density modulator

1999-03-08

2001-11-13

Chin, Stephen (Department: 2734)

Pulse or digital communications

Pulse number modulation

C375S238000, C375S239000, C375S354000, C332S112000, C332S127000

Reexamination Certificate

active

06317457

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pulse density modulator, and more particularly, to a pulse density modulation (PDM) device employed in a portable telephone.
2. Description of the Related Art
There has been proposed a PDM device which performs a modulation process by changing a pulse density per unit time. This PDM device is provided in order to adjust the frequency of a pseudo noise (PN) code generated in a reception side of, for instance, a portable telephone of the code division multiple access (CDMA) system. By employing
FIG. 1
, the circuit constitution of a receiving system in such a portable telephone will be specifically described as follows.
A portable telephone
1
receives a transmission signal which is subjected to a spread spectrum modulation with a pseudo noise code and then transmitted, through an antenna
2
, and inputs a reception signal S
1
to a reception part
3
. The reception part
3
performs a prescribed signal process such as a frequency conversion on the reception signal S
1
, and outputs a reception signal S
2
thus obtained to a multiplier
4
.
The multiplier
4
multiplies the reception signal S
2
by a pseudo noise (PN) code S
3
supplied from a pseudo noise (PN) code generator
5
(that is, an exclusive OR operation) in order to perform an inverse diffusion, and outputs a reception signal S
4
thus obtained to a decoding part
6
and a frequency error correction block
7
. The decoding part
6
performs a decoding process on the reception signal S
4
in order to generate a baseband signal S
5
and outputs the baseband signal S
5
to a subsequent circuit (not shown).
The frequency error correction block
7
is designed to input the reception signal S
4
to a frequency error detection part
8
. The frequency error detection part
8
detects a frequency error between the reception signal S
2
and the PN code S
3
on the basis of the reception signal S
4
which has been multiplied by the PN code S
3
, and outputs the resultant frequency error as frequency error data SE to a PDM part
9
corresponding to the above-described PDM device. The PDM part
9
performs a pulse density modulation on the frequency error data SE based on a clock signal S
7
supplied from a frequency divider
10
in order to generate PDM waveform data SH, and outputs the PDM waveform data SH to a low-pass filter (LPF)
11
.
The LPF
11
extracts a direct current component from the PDM waveform data SH to generate control voltage S
9
and outputs the control voltage S
9
to a voltage control crystal oscillator (VCXO)
12
. The VCXO
12
generates a transmission signal S
10
while changing a transmission frequency in accordance with the control voltage S
9
supplied, and outputs the transmission signal S
10
to the frequency divider
10
. The frequency divider
10
divides the frequency of the transmission signal S
10
in accordance with a predetermined number of frequency divisions so as to generate a clock signal S
7
, and outputs the clock signal S
7
to the PN code generator
5
and the PDM part
9
. The PN code generator
5
generates the PN code S
3
based on the clock signal S
7
supplied from the frequency divider
10
and outputs the PN code S
3
to the multiplier
4
.
The frequency error correction block
7
generates the clock signal S
7
based on the reception signal S
4
multiplied by the PN code S
3
, and supplies the clock signal S
7
to the PN code generator
5
. Thereby, the frequency of the PN code S
3
generated in the PN code generator
5
is controlled so as to correspond to the frequency of the PN code at a transmission side included in the reception signal S
2
.
As illustrated in
FIG. 2
, the PDM part
9
comprises a count circuit
20
, a basic waveform synthesis circuit
21
and a PDM waveform synthesis circuit
22
. The PDM part
9
is designed to input the clock signal S
7
supplied from the frequency divider
10
(
FIG. 1
) to the count circuit
20
. The count circuit
20
composed of a binary count circuit of “n” bits, counts the clock signal S
7
to generate count data SA of “n” bits and outputs the count data SA to the basic waveform synthesis circuit
21
. In this case, the cycle of each bit forming the count data SA is composed of multiples of the cycle of the clock signal S
7
.
As shown in
FIG. 3
, the basic waveform synthesis circuit
21
outputs the least significant bit (LSB) data SA
0
of the supplied count data SA of “n” bits as the most significant bit (MSB) data SB
n−1
of basic waveform data to the PDM waveform synthesis circuit
22
as it is, while inputting the bit data SA
0
to an inverter A
0
. Further, the basic waveform synthesis circuit
21
inputs bit data SA
1
of a column one bit higher than the least significant bit of the count data SA, to an AND circuit B
1
and an inverter A
1
. In the same way, the basic waveform synthesis circuit
21
is designed to input bit of the bit data SA to the corresponding AND circuits B and inverters A. In this connection, the basic waveform synthesis circuit
21
inputs the most significant bit data SA
n−1
of the count data SA to an AND circuit B
n−1
.
The inverter A
0
inverts the polarity of the bit data SA
0
and outputs inverter output data SC
0
thus obtained to the AND circuit B
1
and an AND circuit C
1
. Further, the inverter A
1
inverts the polarity of the bit data SA
1
and outputs inverter output data SC
1
thus obtained to the AND circuit C
1
. In the same way, the inverter A afterward inverts the polarity of the bit data SA and outputs inverter output data SC thus obtained to corresponding AND circuits C.
The AND circuit C
1
takes the AND of the inverter output data SC
0
obtained by inverting the polarity of the count data SA
0
of the least significant bit and the inverter output data SC
1
obtained by inverting the polarity of the bit data SA
1
of a column one bit higher than the least significant bit, and then outputs AND output data SD
1
thus obtained to an AND circuit B
2
and an AND circuit C
2
(not shown). In the same way, the AND circuit C afterward takes the AND of AND output data SD outputted from the AND circuit C of a column one bit lower than that of it and inverter output data SC outputted from the inverter A, and then outputs AND output data SD thus obtained to the AND circuit B and the AND circuit C of a column one bit higher than that of it. In this connection, an AND circuit C
n−2
takes the AND of AND output data SD
n−3
outputted from an AND circuit C
n−3
and inverter output data SC
n−2
outputted from an inverter A
n−2
, and outputs AND output data SD
n−2
thus obtained to the AND circuit B
n−1
.
The AND circuit B
1
takes the AND of the inverter output data SC
0
and the bit data SA
1
, and outputs the computed result to the PDM waveform synthesis circuit
22
as bit data SB
n−2
of a column one bit lower than the most significant bit of the basic waveform data. In addition, the AND circuit B
2
takes the AND of the AND output data SD
1
and count data SA
2
, and outputs the computed result to the PDM waveform synthesis circuit
22
as bit data SB
n−3
of a column two bits lower than the most significant bit. In such a way, the AND circuit B takes the AND of the AND output data SD and the count data SA, and outputs the computed result to the PDM waveform synthesis circuit
22
as basic waveform data SB of a desired column.
As shown in
FIG. 4
, the PDM waveform synthesis circuit
22
inputs the the least significant bit data SB
0
of the basic waveform data SB to an AND circuit D
0
, and inputs the bit data SB
1
of a column one bit higher than the least significant bit to an AND circuit D
1
. In this manner, the PDM waveform synthesis circuit
22
inputs the bits of the basic waveform data SB to corresponding AND circuits D.
The PDM waveform synthesis circuit
22
is supplied the frequency error data SE from the frequency error detection part
8
. The PDM waveform synthesis circuit
22
inputs the least significant bit data S

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