Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1998-09-08
2001-02-06
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S546000
Reexamination Certificate
active
06184744
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an internal power supply voltage generation circuit for generating an operating power supply voltage used by internal circuitry within a device, and more particularly, to an internal power supply voltage-down converter for down-converting an external power supply voltage to generate an internal power supply voltage as the operating power supply voltage.
2. Description of the Background Art
It is effective to reduce the operating power supply voltage for the purpose of reducing power consumption. With reduction of the power supply voltage, the charging/discharging current of a load capacitance becomes lower. Therefore, reducing the power supply voltage allows the power consumption to be reduced in proportion to the square of the voltage reduction ratio (load resistance such as interconnection resistance is constant). For example, in the case of a general-purpose memory that is widely used, the gate length of a transistor used in internal circuitry is scaled-down to the vicinity of the limit in microminiaturization for each generation for speeding up, to improve the integration density and operation speed. By using an on-chip voltage drop circuit, external power supply voltage is down-converted to generate an internal power supply voltage for the memory. The down-converted internal power supply voltage prevents dielectric breakdown and the like of a microminiaturized transistor, so that higher reliability and lower power consumption by reduction in voltage can be realized. The usage of this on-chip voltage drop circuit allows the externally supplied power supply voltage to be equal to the power supply voltage of an externally provided LSI of general usage. Therefore, a system can be developed with a single power source.
This voltage-drop system is also characterized in that, when the down-converted voltage is set constant at a level sufficiently lower than the external power supply voltage, the constant level is maintained even in the event of variation in the external power supply voltage to allow stable operation of internal circuitry.
FIG. 13
shows an example of a structure of a conventional internal power supply voltage generation circuit. Referring to
FIG. 13
, a conventional internal power supply voltage generation circuit includes a reference voltage generation circuit RG receiving current from an external power supply node EXV as an external power supply source that supplies externally applied power supply voltage ExtVcc for generating a reference voltage Vref, a subamplifier SA for supplying a current from external power supply node EXV to an internal power supply line IVL according to a result of comparison between reference voltage Vref from reference voltage generation circuit RG and an internal power supply voltage IntVcc on internal power supply line IVL, and a main amplifier MA activated, when an activation control signal ACT that is activated during operation of internal circuitry (not shown) is activated, for supplying current from external power supply node EXV to internal power supply line IVL according to the result of comparison between reference voltage Vref and internal power supply voltage IntVcc.
The current supply ability of main amplifier MA is set sufficiently greater than the current supply ability of subamplifier SA. When internal power supply voltage IntVcc on internal power supply line IVL is consumed during operation of internal circuitry, main amplifier MA operates at high speed to supply a current with great drivability to suppress reduction in internal power supply voltage IntVcc.
Reference voltage generation circuit RG includes a constant current circuit CCS for generating a constant current i independent of external power supply voltage ExtVcc, and a current/voltage converter CVC for converting the current of constant current circuit CCS into voltage to generate reference voltage Vref.
Constant current circuit CCS includes a p channel MOS (insulated gate field effect) transistor P
1
connected between external power supply node EXV and a node ND
1
and having a gate connected to node ND
1
, a resistor R having one end connected to external power supply node EXV, a p channel MOS transistor P
2
connected between resistor R and a node ND
2
and having a gate connected to node ND
1
, an n channel MOS transistor N
1
connected between node ND
1
and the ground node and having its gate connected to node ND
2
, an n channel MOS transistor N
2
connected between node ND
2
and the ground node and having its gate connected to node ND
2
, and a p channel MOS transistor P
3
for supplying a current from external power supply node EXV according to the level of the voltage on node ND
1
. MOS transistors N
1
and N
2
form a current mirror circuit. The absolute value of a threshold voltage VTP
1
of MOS transistor P
1
is set greater than the absolute value VTP
2
of the threshold voltage of MOS transistor P
2
. The operation will be described.
When MOS transistors N
1
and N
2
have the same size, a current of the same magnitude flows through MOS transistors N
1
and N
2
. Therefore, a current of the same magnitude also flows through MOS transistors P
1
and P
2
. When MOS transistors P
1
and P
2
are identical in size, a voltage VR expressed by the following equation is applied across resistor R from the condition that the saturation currents of MOS transistors P
1
and P
2
are equal to each other.
VR=ExtVcc−
(|
VTP
1|-|
VTP
2|)
Therefore, a current IR flowing through resistor R is represented by the following equation.
IR=
(
ExtVcc−VR
)/
RR=
(|
VTP
1|-|
VTP
2|)/
RR
RR indicates the resistance of resistor R. MOS transistors P
1
and P
3
form a current mirror circuit. Therefore, the mirror current of current IR flowing through MOS transistor P
1
flows through MOS transistor P
3
.
MOS transistors P
4
-P
6
receive the ground voltage at respective gates and function as a resistor to generate a voltage according to the current supplied from MOS transistor P
3
. Therefore, reference voltage Vref has a level determined by the channel resistances of MOS transistors P
4
-P
6
and the threshold voltages of MOS transistors P
1
and P
2
. As a result, reference voltage Vref maintains a constant level independent of external power supply voltage ExtVcc (provided that external power supply voltage ExtVcc is higher than a predetermined voltage level).
Main amplifier MA includes a comparator CMM comparing reference voltage Vref and internal power supply voltage IntVcc on internal power supply line IVL, and a current drive transistor DRM formed of a p channel MOS transistor connected between external power supply node EXV and internal power supply line IVL for supplying a current from external power supply node EXV to internal power supply line IVL in accordance with an output signal from comparator CMM. Comparator CMM includes a p channel MOS transistor P
7
connected between external power supply node EXV and a node NDA and having its gate connected to a node NDB, a p channel MOS transistor P
8
connected between external power supply node EXV and node NDB and having its gate connected to node NDB, an n channel MOS transistor N
3
connected between nodes NDB and NDC and receiving reference voltage Vref at its gate, an n channel MOS transistor N
4
connected between nodes NDB and NDC and having its gate connected to internal power supply line IVL, and an n channel MOS transistor N
5
connected between the ground node and node NDC and receiving activation control signal ACT at its gate.
Main amplifier MA further includes a p channel MOS transistor P
9
connected between external power supply node EXV and the gate of current drive transistor DRM and receiving activation control signal ACT at its gate. The operation of main amplifier MA will be described briefly.
When activation control signal ACT is at an L level (logical low) of an inactive state, MOS transistor
5
is off. The current
Kim Jung Ho
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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