Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2000-09-28
2001-11-27
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S136000
Reexamination Certificate
active
06323798
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a switched capacitor type digital-analog converter, in which a selective activation of a capacitor enables a digital signal to be converted into an analog signal.
2. Description of the Related Art
A liquid crystal display (LCD) panel is used in a display of a note type computer. The LCD panel is also used as a monitor for a desktop type computer. A monitor comprising the LCD panel (LCD type monitor) is used as a variation of a CRT type monitor. A specification similar to that of the CRT is established for the LCD panel comprised by the LCD type monitor. The specification implies, for example, a screen size, a detailed degree, an image quality, a view angle and a gradient. It is necessary to satisfy the specification at a low cost in order that the LCD type monitor is popularized as the variation of the CRT type monitor.
A thin film transistor (TFT) type drive circuit (module) to drive a liquid crystal is used in the LCD panel.
FIG. 1
shows the configuration of a known TFT type LCD module. An LCD module
120
in
FIG. 1
is provided with a y correction circuit
121
, a signal converter
122
, a source driver
123
, a gate driver
124
and an LCD panel
125
. An image signal (IMS) from a computer is applied to the signal converter
122
.
FIG. 2
shows the configuration of a known LCD panel. An LCD panel
125
in
FIG. 2
is provided with a plurality of transistor circuits
130
. The transistor circuit
130
is composed of a transistor
131
and a capacitor
132
.
FIG. 3
shows the configuration of a known source driver. A source driver
123
in
FIG. 3
is composed of a shift register SReg, a data register DReg, a data latch DLat and a digital-analog converter DAC. To the source driver
123
, a start signal SS, an outputting timing signal TS, a digital input signal SID and a reference voltage RV is applied. From the source driver
123
, a cascade output signal OUT is outputted.
A fast operation and a high drive performance are set for the illustrated source driver
123
(TFT drive circuit) in order to satisfy the screen size and the detailed degree. A dynamic range between 10 and 15 V is set for the TFT drive circuit, in order to satisfy the image quality and the view angle. A digital-analog conversion performance of at least 8 bits is set for the TFT drive circuit in order to satisfy the specification with regard to the gradient.
FIG. 4
shows an operation of a dot inversion drive mode of the known TFT drive circuit.
FIG. 4
shows an operation in which a plus and a minus are inverted for each dot.
A common voltage Vcom is kept constant in the dot inversion drive mode. A voltage VLCD which is applied to a liquid crystal is changed between a positive side voltage V+ and a negative side voltage V− with the common voltage Vcom as a boundary. The positive side voltage V+ is a drive voltage higher than the common voltage Vcom. The negative side voltage V− is a drive voltage lower than the common voltage Vcom.
In the dot inversion drive mode, an 8-bit digital-analog converter is used for each of the positive side voltage V+ (f
1
, f
3
, . . . )and the negative side voltage V− (f
2
, . . . ) for the frame F
1
and F
2
.
FIG. 5
shows an operation of a line inversion drive mode of the known TFT drive circuit.
FIG. 5
shows an operation in which a plus and a minus are inverted for each line.
In the line inversion drive mode, a common voltage Vcom is varied for each line. When this common voltage Vcom is varied, a voltage VLCD which is applied to the liquid crystal is set at a positive side voltage V+ and a negative side voltage V−. The variation range between the positive side voltage V+ and the negative side voltage V− is equal to the common voltage Vcom. The positive side voltage V+ is a drive voltage when the common voltage Vcom is low. The negative side voltage V− is a drive voltage when the common voltage Vcom is high.
In the line inversion drive mode, one 8-bit digital-analog converter is used in the whole of the positive side voltage V+ (f
1
, f
3
, . . . )and the negative side voltage V− (f
2
, . . . ) for frame F
1
, F
2
.
A TFT drive circuit operated at the dot inversion drive mode employs a digital-analog converter equal to two times the TFT drive circuit operated at the line inversion drive mode.
FIG. 6
shows a known digital-analog converter. The digital-analog converter in
FIG. 6
is a switched capacitor type.
A switched capacitor type digital-analog converter
170
is provided with a high voltage process HP. Further more, the converter
170
is provided with an input capacitor
171
-
0
, shared input capacitors
171
-
1
to
171
-n, an output capacitor
172
, switches
173
-
1
to
173
-n, switches
174
-
1
to
174
-n, an input switch
175
, a reference voltage switch
176
, a short-circuit switch
177
, an output switch
178
and an operational amplifier
179
.
A first voltage V
1
is applied to the switches
173
-
1
to
173
-n. Outputs of the switches
173
-
1
to
173
-n are connected to inputs of the shared input capacitors
171
-
1
to
171
-n. Outputs of the shared input capacitors
171
-
1
to
171
-n are connected to an inversion input of the operational amplifier
179
. The outputs of the shared input capacitors
171
-
1
to
171
-n are connected to an input of the short-circuit switch
177
. An output of the output capacitor
172
is connected to an output of the operational amplifier
179
. An output of the short-circuit switch
177
is connected to the output of the operational amplifier
179
. And, the output of the operational amplifier
179
is connected to an input of the output switch
178
.
A second voltage V
2
is applied to the input switch
175
. An output of the input switch
175
is connected to an output of the reference voltage switch
176
. An output of the input switch
175
is connected to an input of the input capacitor
171
-
0
. The output of the input switch
175
is connected to inputs of the switches
174
-
1
to
174
-n. Outputs of the switches
174
-
1
to
174
-n are connected to the inputs of the shared input capacitors
171
-
1
to
171
-n. An output of the input capacitor
171
-
0
is connected to the inversion input of the operational amplifier
179
. A reference voltage Vr is applied to an input of the reference voltage switch
176
. The input of the reference voltage switch
176
is connected to a non-inversion input of the operational amplifier
179
. The switch has the configuration in which a p-channel transistor and an N-channel transistor are combined. The switch is set ON if the input is at a high level.
The switched capacitor type digital-analog converter
170
corresponds to an output of a positive side voltage for Vcom and an output of a negative side voltage for Vcom. The first voltage V
1
is higher than the second voltage V
2
. Capacitances C
0
, C
1
of the capacitors
171
-
0
,
171
-
1
are a standard capacitance C. A capacitance C
2
of the capacitor
171
-
2
is C
2
=2×C. A capacitance C
3
of the capacitor
171
-
3
is C
3
=2×2×C. A capacitance of the capacitor
171
-n is Cn=2
n−1
×C(n≦1). A capacitance Cc of the output capacitor
172
is Cc=2
n
×C.
If the switched capacitor type digital-analog converter
170
is at an output state, the short-circuit switch
177
and the reference voltage switch
176
are set OFF, and the output switch
178
and the input switch
175
are set ON. If the switches
173
-
1
to
173
-n are set ON, the switches
174
-
1
to
174
-n are set OFF. If the switches
173
-
1
to
173
-n are set OFF, the switches
174
-
1
to
174
-n are set ON.
An output voltage Vo can be represented by the equation (1):
Vo=2×Vr−(V
2
+(&agr;/2
n
)×(V
1
−V
2
)) (1)
Here, &agr; is a value of an inputted input data, and indicates a numeral between 0 and (2
n
−1) . In a case of 8 bits, it indicates &agr;=0 to 255.
If
NEC Corporation
Wamsley Patrick
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