Semiconductor memory device with a plurality of memory blocks

Details Semiconductor memory device with a plurality of memory blocks Semiconductor memory device with a plurality of memory blocks

2000-09-25

2001-11-06

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189011, C365S189080, C365S191000, C365S205000, C365S202000

Reexamination Certificate

active

06314045

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to semiconductor memory devices having a plurality of banks.
2. Description of the Background Art
Conventionally there exist semiconductor memory devices having a plurality of banks. In such semiconductor memory devices, each bank includes a plurality of memory cells arranged in rows and columns, and a plurality of words lines corresponding to a plurality of rows and a plurality of bit lines corresponding to a plurality of columns. The banks can be activated and inactivated (or precharged) substantially independent of each other.
In such a semiconductor memory device, initially at a selected bank the data on a bit line pair connected to a selected word line is differentially amplified by a sense amplifier. Then, when a write/read instruction is received, a designated bit line pair and a data input/output line pair are electrically connected together. Thus data is written to a selected memory cell or data is read from a selected memory cell.
A data input/output line pair and a bit line pair are not allowed to be electrically connected together until a predetermined period of time elapses after a sense amplifier is activated.
This is because a period of time is required for the sense amplifier to sufficiently amplify a slight potential difference between the paired bit lines. Allowing a sense amplifier to amplify a potential difference between paired bit lines for longer periods of time ensures that the sense amplifier more reliably amplifies the potential difference between the paired bit lines.
On the other hand, according to a specification of the semiconductor device a read/write command can be input after a defined period tRCD elapses following the activation of a bank. As such, a bit line pair and a data input/output line pair must be allowed to be connected together if the defined period of time tRCD is satisfied.
As such, in a conventional semiconductor memory device a bit line pair and a data input/output line pair are connected together in response to a control signal (an interlock signal) output from a connection control circuit
900
shown in FIG.
10
.
As shown in
FIG. 10
, connection control circuit
900
includes a delay stage
901
configured of inverters
902
A,
902
B, . . . and
902
M, an inverter
903
, and an NAND circuit
904
. Inverters
902
A,
902
B, . . . and
902
M are connected in series. Inverter
902
A receives a sense amplifier activation signal &phgr;N. Delay stage
901
delays sense amplifier activation signal &phgr;N to output a signal &phgr;X. NAND circuit
904
receives sense amplifier activation signal &phgr;N and signal &phgr;X. Inverter
903
inverts an output from NAND circuit
904
and outputs an interlock signal CE.
Sense amplifier activation signal &phgr;N is provided to activate a sense amplifier. When a row select operation starts, a selected bank's sense amplifier activation signal &phgr;N is driven high, which is received by a sense amplifier, which amplifies a potential difference between paired bit lines connected thereto.
As shown in
FIG. 11
, when sense amplifier activation signal &phgr;N is driven high and a delay time (&Dgr;D) provided by delay stage
901
then elapses, interlock signal CE is driven high.
When interlock signal CE is driven high, a selected column (a bit line pair) and a data input/output line pair are electrically connectable together via a gate (not shown). As such, when a sense amplifier is activated and a predetermined period of time &Dgr;D then elapses a bit line pair and a data input/output line pair can be connected together.
However, if the conventional connection control circuit
900
is used interlock signal CE is activated at a timing determined depending on delay stage
901
. As such, interlock signal CE would be activated at an offset timing depending on a condition of process, temperature or voltage. Thus it has been difficult to satisfy the defined period of time tRCD as well as ensure a sufficient margin.
SUMMARY OF THE INVENTION
The present invention has been made to overcome the disadvantage described above and contemplates a semiconductor memory device capable of connecting a bit line pair and a data input/output line pair at an optimal timing.
In accordance with the present invention, a semiconductor memory device includes a plurality of memory blocks each having a plurality of memory cells arranged in rows and columns, and a plurality of word lines and a plurality of bit line pairs; a data input/output line for allowing the plurality of memory blocks to communicate data externally; a select circuit responsive to an address signal for selecting a memory block; a control circuit providing control for activating a selected memory block and reading data from the selected memory block or writing data to the selected memory block; a gate receiving an active control signal to operate to connect a selected memory block and a data input/output line together; and a connection control circuit controlling an operation of the gate, wherein the connection control circuit sets the control signal inactive until there is received a read/write command designating a data read or a data write.
Preferably, the semiconductor memory device further includes a plurality of sense amplifiers each responsive to an active sense amplifier activation signal for differentially amplifying a potential difference between paired bit lines corresponding thereto, and the control circuit, which activates a selected memory block, includes a circuit activating a sense amplifier activation signal corresponding thereto and the connection control circuit sets the control signal inactive until a read/wlite command is input after a sense amplifier activation signal is activated.
Preferably, the data input/output line includes a plurality of local input/output lines and a global input/output line shared by the plurality of memory blocks, and the gate includes a plurality of select gates provided for the plurality of local input/output lines, respectively, and a plurality of switches arranged between their respective local input/output lines and the global input/output line, wherein the plurality of select gates are each responsive to the control signal for operating to allow a selected memory block and a local input/output line corresponding thereto to be electrically connectable together and the plurality of switches each selectively connect a local input/output line corresponding to a selected memory block and the global input/output line together when a read/write command is received.
Preferably, the semiconductor memory device also includes a command decoder decoding an input command, wherein the command decoder generates a timing signal when a read/write command is received, the select circuit when it receives the timing signal activates a column bank address designating a memory block subjected to a data read or a data write designated by an address signal, and the connection control circuit includes a logic circuit activating the control signal when it receives an active sense amplifier activation signal and a column bank address.
In particular, the logic circuit is configured of a flip flop receiving the sense amplifier activation signal and the column bank address.
Thus in the present invention the semiconductor memory device with a plurality of banks can have a selected bank and a data input/output line disconnected until a read/wlite command for the selected bank is received after a sense amplifier is activated. When the read/write command is applied a selected bank corresponding thereto and a data input/output line can be connected together.
Thus, connecting a data input/output line and a bit line together can be controlled at an optimal timing.
Furthermore, the flip flop configuring the connection control circuit generating the connection control signal (the interlock signal) input to the gate controlling the connection of a data input/output line and a bit line, allows the c

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