Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
1998-04-06
2001-10-30
Kelley, Chris (Department: 2713)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
Reexamination Certificate
active
06310921
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital signal processing and in particular to a media processing apparatus which decompresses compressed video data and compressed audio data, and can also compress video data and audio data and perform graphics processing.
2. Description of the Related Art
With the establishment of compressing/decoding techniques for digital video data and the improvements in LSI (Large Scale Integration) technology in recent years, various media processing circuits, such as for a decoder decoding compressed video and audio data, an encoder compressing video and audio data, and graphics processing, have come to be highly valued.
As a first related art, there is an AV (Audio Visual) decoder which decodes video data and audio data compressed according to MPEG (Moving Picture Experts Group) standard (see Japanese Laid-Open Patent Application No. 8-1116429). This AV decoder decodes both video data and audio data using one signal processing unit.
FIG. 1
shows a representation of the decode processing performed by this AV decoder. In
FIG. 1
, the vertical axis denotes time and the horizontal axis denotes calculation amount.
Taking a larger view along the vertical axis, video data and audio data are alternately decoded since the AV decoder decodes both video data and audio data using the same hardware. As shown in
FIG. 1
, the operation for the video decoding is divided into sequential processing and block processing. In the sequential processing, non-block data is decoded, that is, various conditions need to be judged, such as for analyzing a header of an MPEG stream. Here, the calculation amount of the sequential processing is small. Meanwhile, in the block processing, variable length codes of the MPEG stream are decoded, and IQ (Inverse Quantization) and IDCT (Inverse Discrete Cosine Transform) are performed in units of blocks. Here, the calculation amount of the block processing is large. The operation for the audio decoding is also divided into sequential processing which requires various condition judgements as in the case with the sequential processing of the video decoding, and decode processing for decoding the core audio data. This decode processing for the core audio data requires higher precision than for decoding the video data, and the processing has to be completed within a limited time. Therefore, the audio data needs to be processed with high precision at high speed, and the calculation amount is large.
Accordingly, the first related art enables the circuitry to be provided on a single chip and realizes an AV decoder which operates at high efficiency using small scale hardware, i.e., one chip.
As a second related art, there is a decoder composed of two chips. One chip is used as a video decoder and the other chip as an audio decoder.
FIG. 2
shows a representation of decode processing performed by the decoder composed of two chips. Both the video decoder and the audio decoder perform sequential processing including various condition judgements, such as header analysis, and block processing mainly for decoding the core data. The video decoder and the audio decoder operate independently, so that both chips can be realized using lower performance chips than in the first related art.
However, these related arts have the following drawbacks. By means of the first related art, the signal processing unit has to decode both video data and audio data, so that high performance is required. That is, the signal processing unit needs to operate using a high speed clock whose frequency is over 100 MHz. As a result, the cost is high, making such processing unit unsuitable for a consumer appliances. To improve the performance without using a high speed clock, a VLIW (Very Long Instruction Word) processor can be used. However, VLIW processors are themselves expensive, and the overall processing will be inefficient unless an additional processor is used to perform the sequential processing.
Meanwhile, the second related art also has a drawback in the high cost due to two processors to be used. A common, standard ordinary low priced processor whose performance is low cannot be used as a video processor nor an audio processor. The video processor is required to process a large quantity of image data in real time. Although the audio processor does not need to perform as many calculations as the video processor, higher precision is required for the audio data than for the video data. Therefore, a low priced processor, or a low-performance processor, does not serve the need for the required performance in decoding either of video data and audio data.
When the media processing circuit is used in an AV decoder provided in a digital (satellite) broadcast tuner (called an STB (Set Top Box)) or a DVD (Digital Versatile/Video Disc), MPEG streams received from a broadcast wave or read from a disc are inputted, the MPEG streams are decoded, and video signals and audio signals are respectively outputted to a display and speakers. This series of processes requires a huge amount of processing. For this reason, there has been increasing demand for a media processing apparatus which can efficiently execute this huge amount of processing.
SUMMARY OF THE INVENTION
It is a primary object for the present invention to provide a media processing apparatus which performs a series of processes, that is, inputting stream data representing compressed image data and compressed audio data, decoding the inputted stream data, and outputting the decoded data, with high performance which the media processing apparatus of the present invention can obtain without operating at high frequency, and accordingly, the cost of manufacturing can be reduced.
Moreover, it is a secondary object for the present invention to provide a media processing apparatus which realizes decoding of compressed video data, encoding of video data, and graphics processing at low cost.
To achieve the stated objects, the media processing apparatus of the present invention inputs a data stream including compressed audio data and compressed video data, decodes data in the inputted data stream, and respectively outputs the decoded audio data and the decoded video data to an external display device and an external audio output device, the media processing apparatus can be made up of: an input/output processing means for performing an input/output processing asynchronously occurring due to an external factor, the input/output processing including inputting the data stream which is asynchronously inputted, storing data in the inputted data stream into a memory, and supplying the data stored in the memory to a decode processing means; and the decode processing means which, in parallel with the input/output processing, performs a decode processing where decoding of the data stream stored in the memory is mainly performed, and the decoded video data and the decoded audio data are stored in the memory, and the input/output processing means reads the decoded video data and the decoded audio data from the memory in accordance with respective output rates of an external display device and an external audio output device, and respectively outputs the read video data and the read audio data to the external display device and the external audio output device.
By means of this structure, the input/output processing means and the decode processing means are respectively charged with the asynchronous processing and the decode processing, in addition to that the input/output processing means and the decode processing means operate in parallel as in the pipeline processing. Therefore, the decode processing means can be devoted to the decode processing, regardless of asynchronous processing. Accordingly, a series of processes including input processing of stream data, decode processing of the inputted data, and output processing of decoded data are executed with efficiency, and full decode (with no frame omitted) processing can be realized using no high speed operation clock.
Here, the decode pr
Hirai Makoto
Kimura Kozo
Kiyohara Tokuzo
Yoshioka Kosuke
Kelley Chris
Matsushita Electric - Industrial Co., Ltd.
Price and Gess
Wong Allen
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