Method for post transistor isolation

Details Method for post transistor isolation Method for post transistor isolation

1997-05-22

2001-02-06

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S624000, C438S626000

Reexamination Certificate

active

06184105

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to fabricating an integrated circuit with field oxide isolation of transistors in the integrated circuit.
BACKGROUND OF THE INVENTION
With increasing levels of integrated circuits in semiconductor chips or dies, such as those with a silicon substrate, several conflicting demands are put on the integrated circuit process. Today's integrated circuits demand high performance and high density, but also require low leakage currents to minimize power consumption. As the layout of the integrated circuit positions the transistors closer and closer together, it becomes increasing difficult to isolate the transistors so that parasitic leakage currents do not result.
Isolation of the transistors is generally accomplished by separating the individual transistors areas with a insulating material such as an oxide of silicon. The isolation, commonly known as field oxidation, is formed by either a LOCOS method in which the transistor area is masked and the isolation area is thermally oxidized, or by a trench isolation method in which an opening is forming in the silicon and filled with insulation. Normally, the trench, which varies in width, is a shallow trench in depth and is known as shallow trench isolation or STI.
The field oxidation is formed before the transistors with both of the LOCOS and STI methods. The STI provides the advantage of using less silicon than LOCOS thereby permitting a greater number of transistors for the same amount of silicon. However, it has been found that the STI degrades the quality of the subsequently thermally grown gate oxide of the transistor, especially at the STI edge, and is still susceptible to leakage along the edge of the STI. Further, the surface of the STIs, both wide and narrow, are simultaneously planarized after formation of the STIs which causes dishing of the wide STIs. In contrast, the LOCOS method does not degrade the quality of the thermally grown oxide gate nor cause junction leakage problems. However, LOCOS does encroach into the transistor areas and does not allow the same number of transistors for the same amount of silicon. Further, LOCOS does not allow scaling of diffusions (e.g., N+ to P+ or N+ to N+ or P+ to P+) without confronting the problem of leakage.
It would be desirable to maximize the use of LOCOS and its non-degrading and non-leakage advantages while maximizing the density advantage of STI without incurring its disadvantages.
SUMMARY OF THE INVENTION
The primary object of the present invention is provide a method of fabricating integrated circuits which increases the packing density of the transistors minimizing the parasitic transistor and leakage problems of STI.
Another object of the present invention is provide a method of fabricating integrated circuits to permit selectivity in the use of STI for isolation.
A further object of the present invention is to provide a method of fabricating integrated circuits with STI without affecting the quality of the gate oxide of the transistors.
These objects are achieved in accordance with the present invention by a method which comprising the following steps:
forming a trench opening in the silicon substrate after the formation of all of the FETs and the LOCOS isolation; and
filling the trench opening with an insulating material.


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