Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
1999-06-25
2001-10-30
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S782000, C257S776000, C257S783000, C257S786000, C257S773000
Reexamination Certificate
active
06310402
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device, and particularly to a layout of input/output cells employed in an ASIC (Application Specific Integrated Circuit) such as a gate array, an embedded array or the like.
2. Description of the Related Art
A semiconductor device, particularly an ASIC, makes various implementation demands according to the purposes of users in a short time, in terms of the time required for the development and manufacturing process. Since the ASIC is fabricated according to the purposes of the users, there is a tendency to use it in a wide variety of products.
The semiconductor devices are formed as the separate products according to the number of pads as follows. Pads are respectively placed at predetermined intervals according to the number of the pads therein. With respect to input/output cells having elements or devices for respectively forming input/output circuits in accordance with the pads, the widths (corresponding to lengths extending in the direction in which the pads are placed) are respectively determined according to the number of the pads and layout intervals between the respective pads. Therefore, even input/output cells that differ with regards to the size of the input/output cell forming region are prepared in the same circuit configuration in accordance with the number of the pads.
Thus, since even devices that differ with regards to the size of the input/output cell forming region are prepared, their fabrication and development are performed correspondingly and their fabrication and development costs are involved. Therefore, the conventional semiconductor devices do not always satisfy a user's demands with ease in terms of time and a reduction in cost.
With a multi-pin configuration of a semiconductor device, it becomes increasingly difficult to place a plurality of pads within a limited pad placement region in a row. As a countermeasure against this difficulty, a so-called zigzag pad arrangement is known in which pads are placed alternately closer to and further from input/output cells.
In this case, wires or interconnections for respectively connecting between the pads that are placed farther from the input/output cell side and the input/output cells become narrow in width, so that the amount of current allowable for each interconnection is reduced. Thus, since the amount of allowable current in this case becomes less than the amount of current allowable for the pads that are placed close to the input/output cell side, limitations are imposed on signals for objects which utilize the pads that are placed farther from the input/output cell side.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device that meets a user's demands in terms of ease and time.
Further, the present invention implements the above object and further provides a reduction in the cost thereof.
Another object of the present invention is to achieve the above object by effectively utilizing input/output cells.
A further object of the present invention is to provide a semiconductor device capable of increasing the amount of current allowable for the interconnections placed between pads and input/output cells thereby to improve the degree of freedom of interconnections.
According to one aspect of this invention, for achieving the above objects, there is provided a semiconductor device comprising a plurality of pads placed at predetermined intervals, and a plurality of input/output cells that respectively have input/output circuit forming elements and that are electrically connected to the elements of any of the plurality of pads same line the widths of input/output cell forming regions extending in the direction of the placement of the plurality of pads are respectively narrower than layout intervals between the plurality of pads further the pads corresponding to a number equivalent to (least common multiple between the width of each input/output cell forming region and the layout interval between the pads) divided by the (layout interval between the pads are respectively connected to elements of any of the input/output cells corresponding to a number equivalent to (least common multiple between the width of each input/output sell forming region and the layout interval between the pads) divided by the (width of each input/output cell forming region.
In the present invention as well, the pads and input/output cells are respectively placed along predetermined sides of the semiconductor device. Pads may be provided even with respect to input/output cells equivalent to the remainder obtained by dividing the number of the plurality of input/output cells extending along the sides by a number corresponding to least common multiple between the width of each input/output cell forming region and the layout interval between the pads) divided by the (width of each input/output cell forming region.
Further, in the present invention, a plurality of pads and non-connected input/output cells may be used as a high-driven driver and protection circuits for a power supply interconnection, etc.
According to another aspect of this invention, for achieving the above objects, there is provided a semiconductor device comprising a plurality of pads that are placed at predetermined intervals and a plurality of input/output cells respectively having input/output circuit forming elements and that are electrically connected to elements of any of the plurality of pads. The plurality of pads comprise a first group placed in the vicinity of the input/output cells and a second group placed so as to be farther away from the first group as viewed from the input/output cells, and each of interconnections for respectively connecting the input/output cells in the second group and their corresponding pads has a multilayer interconnection structure.
In the present invention as well, the width of the interconnection for connecting between each input/output cell in the second group and its corresponding pad may be set narrower than that of an interconnection for connecting between each input/output cell in the first group and its corresponding pad.
Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.
REFERENCES:
patent: 5324985 (1994-06-01), Hamada et al.
patent: 5334872 (1994-08-01), Ueda et al.
patent: 5391923 (1995-02-01), Harada
patent: 5466952 (1995-11-01), Aeba
patent: 5506444 (1996-04-01), Chikawa et al.
patent: 5719445 (1998-02-01), McClure
Abraham Fetsum
OKI Electric Industry Co., Ltd.
Rabin & Berdo P.C.
LandOfFree
Semiconductor die having input/output cells and contact pads... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor die having input/output cells and contact pads..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor die having input/output cells and contact pads... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2605154