Self-aligned LDD lateral DMOS transistor with high-voltage inter

Details Self-aligned LDD lateral DMOS transistor with high-voltage inter Self-aligned LDD lateral DMOS transistor with high-voltage inter

1988-12-15

1991-10-08

Larkins, WIlliam D.

357 234, H01L 29784

Patent

active

050558960

ABSTRACT:
Our invention is an annular-shaped or rectangular-shaped lateral DMOS device which overcomes the problems of field crowding caused by a high voltage drain interconnect line creating an increased electric field in the vicinity of a drift region/channel interface. To prevent the interconnect line voltage from causing field crowding, the drift region is discontinued for a portion under the interconnect line so as to make that part of the DMOS device inactive. Therefore, the portion of the DMOS device under the high voltage drain interconnect is not subject to field crowding and in no way reduces the breakdown voltage of the DMOS device. In one embodiment of this invention, a field oxide region is formed between a channel region and a drain region in an area under and extending out from under where a high voltage drain interconnect is to be formed. Impurities implanted in a subsequent impurity implant process to form the drift region will, therefore, be prevented from entering the silicon under the field oxide region.

REFERENCES:
patent: 4819045 (1989-04-01), Murakami
patent: 4890146 (1989-12-01), Williams et al.

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