Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-09-02
2001-11-06
Vincent, David R. (Department: 2732)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C711S221000, C709S238000
Reexamination Certificate
active
06314099
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an address match determining device which can be incorporated into a communication control system such as a gateway or a control area network (CAN) in which each communication terminal can receive packets with different addresses, for determining whether or not the address code included in a packet is available, and to a communication control system including such an address match determining device. The invention also relates to a method of determining whether or not the address code included in a packet is available.
2. Description of the Prior Art
Referring now to
FIG. 31
, there is illustrated a block diagram showing the structure of a prior art communication control system. The communication control system includes a communication control LSI
1
for determining whether or not the address within a packet applied thereto match with available addresses of packets which are allowed to be transferred, a CPU
2
for controlling the communication control LSI
1
, and a memory
3
for storing the packet to be transferred and the available addresses of packets which are allowed to be transferred.
Referring next to
FIG. 32
, there is illustrated a block diagram showing the detailed structure of the communication control LSI
1
of FIG.
31
. The communication control LSI
1
comprises a received-address latch
4
for latching and temporarily storing the address code within a packet, a number of address-to-be-compared latches
5
for storing available addresses to be compared with the address stored in the received-address latch
4
, a number of logical circuits
9
each for comparing the address stored in the received-address latch
4
with one available address stored in one address-to-be-compared latch
5
, and an OR gate
13
which furnishes an address match signal when any one of the plurality of logical circuits
9
detects an address match.
In operation, when the communication control LSI
1
receives a packet, it extracts an address code from the packet and stores the address code into the received-address latch
4
. On the other hand, the addresses of packets which are allowed to be transferred are prestored in the plurality of address-to-be-compared latches
5
. In a communication system wherein there are 2048 possible addresses any one of which a packet to be transmitted via the transmission line have, if only 256 different addresses of them are available, 256 address-to-be-compared latches and 256 logical circuits are needed.
When the latched address code is temporarily stored in the received-address latch
4
, each of the plurality of logical circuits
9
compares the latched address with one available address and then determines whether the latched address match with the available address. The OR gate
13
furnishes an address match signal to the CPU
2
when any one of the plurality of logical circuits
9
detects an address match. Otherwise, the OR gate
13
furnishes no address match signal. When the CPU
2
receives the address match signal from the OR gate
13
of the communication control LSI
1
, it enables the communication control LSI
1
to transfer the packet to another communication device. In contrast, when the OR gate
13
furnishes no address match signal, the CPU
2
disables the packet transfer.
FIG. 33
shows a flow diagram showing an address comparison processing which is all carried out by the CPU
2
according to a software program. The amount of the address comparison processing is increased with an increase in the number of available addresses to be compared with the address latched into the received-address latch
4
(see the program list shown in FIG.
34
), resulting in a greater burden of the address comparison processing put upon the CPU
2
, which interferes with other processing such as the reception of packets. The number of available addresses to be compared with the address latched must be limited by a large margin.
A problem with the prior art communication control system which is so constructed is thus that a required number of address-to-be-compared latches and logical circuits, the number of which corresponds to the number of available addresses, must be provided, and therefore, if the number of available addresses any one of which each packet can have is relatively large, the size of the communication control LSI
1
is increased and the cost of the communication control LSI rises.
A second problem is that when it is required to change the number of available addresses, the communication control LSI
1
cannot support such the requirement and hence there is no alternative but to change the design of the communication control LSI
1
.
Another problem is that the burden of the address comparison processing put upon the CPU
2
is increased in proportional to an increase in the number of available addresses to be compared with the address latched into the received-address latch, and therefore the speed with which the CPU can perform the address comparison processing is decreased exceedingly.
SUMMARY OF THE INVENTION
The present invention is made to overcome the above problems. It is therefore an object of the present invention to provide an address match determining device which can perform address comparing processing at a high speed without the need to increase its size even when the number of available addresses any one of which each packet that is allowed to be transferred can have is relatively large, and a communication control system including such an address match determining device.
It is another object of the present invention to provide a method capable of performing address comparing processing at a high speed.
In accordance with an aspect of the present invention, there is provided an address match determining device comprising: a storage unit for storing a matrix or table having a plurality of elements each of which is a 1-bit address match determination data indicating whether or not a corresponding N-bit address code is available, and is distinguished by a pair of a first index composed of the m most significant or high-order m bits of the corresponding address code and a second index composed of the remaining lowest or low-order (N−m) bits of the corresponding address code; an extract unit for receiving an N-bit address code included in a packet to be transmitted by way of a transmission line, and for extracting the high-order m bits and remaining low-order (N−m) bits from the address code received; and a search and determination unit for searching through the table stored in the storage unit for one 1-bit address match determination data specified by the first index composed of the extracted high-order m bits and the second index composed of the extracted low-order (N−m) bits, and for determining whether the 1-bit address match determination data searched for indicates that the received address code is available.
In accordance with a preferred embodiment of the present invention, the search and determination unit includes a retrieving unit for retrieving a row or column of plural 1-bit address match determination data which is specified by the first index composed of the extracted high-order m bits from the table stored in the storage unit, and a determination unit for determining whether one of the plural 1-bit address match determination data corresponding to the second index composed of the extracted low-order (N−m) bits indicates that the received address code is available.
Alternatively, the search and determination unit includes a retrieving unit for retrieving a row or column of plural 1-bit address match determination data which is specified by the second index composed of the extracted low-order (N−m) bits from the table stored in the storage unit, and a determination unit for determining whether one of the plural 1-bit address match determination data corresponding to the first index composed of the extracted high-order m bits indicates that the received address code is available.
In acco
Fujisawa Yukio
Gottschalk Christoph
Loch Hans-Michael
Miyamoto Kazutoshi
Burns Doane , Swecker, Mathis LLP
Mitsubishi Electric System LSI Design Corporation
Vincent David R.
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