Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-02-01
2001-02-13
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000, C327S039000, C326S094000
Reexamination Certificate
active
06188257
ABSTRACT:
BACKGROUND
The present invention concerns security protection within an integrated circuit design and pertains particularly to power-on-reset logic with secure power down capability.
For some processing applications, it is essential to operate in a secure environment so that operations cannot be probed or altered. In the prior art, various methods have been used to provide for a secure processing environment.
A power-on-reset cell provides a known state for a device when power is applied. Initializing to a known state is critical to a secure processor chip. This is used to ensure the initial state of the processing chip is always defined. Therefore, the integrity of the power-on-reset cell is imperative for the security of the system.
However, there are test strategies that require that all elements of an integrated circuit to be powered down into a low power state to test the chip at time of manufacture (called IDDQ testing). Since during IDDQ testing the state of any register or information on the integrated circuit cannot be defined at power-on time, it is desirable to place the power-on-reset cell into a power-down state in order to allow testing.
However if an external pin is used to power down the power-on-reset cell, the external pin could potentially be used by an attacker to bypass the power-on-reset cell and bring the integrated circuit up into an undefined initial state. It is desirable, therefore, to find a way to allow a power-on-reset cell to be powered down for testing while assuring that the power-on-reset feature of the integrated circuit cannot be bypassed by an attacker.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, power-on-reset logic is included within an integrated circuit. The power-on-reset logic includes a power-on-reset cell. The power-on-reset cell causes a reset signal to be issued upon a power signal being connected to the integrated circuit. The power-on-reset cell includes a power down input connected to a power-down line. When a power-down signal is placed on the power-down line, the power-on-reset cell is inactivated so that the power-on-reset cell does not cause the reset signal to be issued upon the power signal being connected to the integrated circuit.
In the preferred embodiment, the power-on-reset logic also includes a logic block connected to the power-down line and to a system clock. The logic block issues a reset when the power-down signal is placed on the powerdown line and the system clock is active. For example, the logic block is a delay (D) flip-flop having a D input connected to the power down line and a clock input connected to the system clock.
To provide further protection, the power-on-reset logic also includes a low-frequency monitor. The low frequency monitor causes the reset signal to be issued when a frequency of the system clock is below a predetermined low-frequency threshold.
The present invention effectively prevents attempts to bypass the power-on-reset feature of an integrated circuit. When the power-on-reset cell is powered down, an attacker cannot clock the integrated circuit without causing a reset that initializes the integrated circuit to a known state. The addition of a low frequency monitor prevents the system clock from being stopped. If the power down is applied before the integrated circuit goes into a test mode (low frequency monitor disable) the integrated circuit will go into a reset state preventing the power-on-reset from being bypassed.
REFERENCES:
patent: 3950654 (1976-04-01), Broedner et al.
patent: 5323066 (1994-06-01), Feddeler et al.
patent: 5778238 (1998-07-01), Hofhine
patent: 5929672 (1999-07-01), Mitani
patent: 5949261 (1999-09-01), Field et al.
Callahan Timothy P.
Englund Terry L.
VLSI Technology Inc.
Weller Douglas L.
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