Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1998-07-15
2001-02-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
Reexamination Certificate
active
06190989
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to integrated circuits and more particularly to enhanced shapes and the fabrication of enhanced shapes for openings or cavities for container capacitors and other structures in integrated circuit devices.
BACKGROUND OF THE INVENTION
In semiconductor fabrication, it is often necessary to create openings or cavities into which selected materials can be deposited. While the invention is primarily discussed with respect to capacitors, it is to be understood that the invention is applicable in all areas of semiconductor fabrication where openings are formed such as in the creation of polysilicon plugs, bit line contacts and various other structures.
Capacitors are used in a wide variety of semiconductor circuits. Capacitors are of special concern in DRAM (dynamic random access memory) memory circuits; therefore, the invention will be discussed in connection with DRAM memory circuits.
DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. A DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a storage capacitor and an access field effect transistor.
FIG. 1
illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells
10
. For each cell, one side of the storage capacitor
14
is connected to a reference voltage, which is typically one half of the internal operating voltage (the voltage corresponding to a logical “1” signal) of the circuit. The other side of the storage capacitor
14
is connected to the drain of the access field effect transistor
12
. The gate of the access field effect transistor
12
is connected to a signal referred to as the word line
18
. The source of the field effect transistor
12
is connected to a signal referred to as the bit line
16
. With the circuit connected in this manner, it is apparent that the word line controls access to the storage capacitor
14
by allowing or preventing the signal (a logic “0” or a logic “1”) on the bit line
16
to be written to or read from the storage capacitor
14
.
DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and increase memory cell density to allow more memory to be squeezed onto a single memory chip. However, it is necessary to maintain a sufficiently high storage capacitance to maintain a charge at the refresh rates currently in use even as cell size continues to shrink. This requirement has led DRAM manufacturers to turn to three dimensional capacitor designs, including trench and stacked capacitors. Stacked capacitors are capacitors which are placed over the access transistor in a semiconductor device. In contrast, trench capacitors are formed in the wafer substrate beneath the transistor. For ease of fabrication and increased capacitance, most manufacturers of DRAMs larger than
4
Megabits use stacked capacitors. Therefore, the invention will be discussed in connection with stacked capacitors but should not be understood to be limited thereto. Use of the invention to fabricate trench, planar or other capacitors is also possible.
One widely used type of stacked capacitor is known as a container capacitor. Known container capacitors are in the shape of an upstanding tube (cylinder) having an oval or circular cross section. The wall of the tube consists of two plates of conductive material such as doped polycrystalline silicon (referred to herein as polysilicon or poly) separated by a dielectric. The bottom end of the tube is closed, with the outer wall in contact with either the drain of the access transistor or a plug which itself is in contact with the drain. The other end of the tube is open (the tube is filled with an insulative material later in the fabrication process). The sidewall and closed end of the tube form a container; hence the name “container capacitor.” Although the invention will be further discussed in connection with stacked container capacitors, the invention should not be understood to be limited thereto.
In a typical fabrication process, capacitors such as stacked container capacitors are formed by patterning a surface to produce an opening or container cell, which is then filled with conductive materials such as hemispherical grained poly (HSG) or the like and with cell dielectric material. The amount of material which can be deposited within the container cell determines the capacitance of the capacitor. The volume of the container cell per given substrate area is therefore very important.
The patterning process of a container cell typically involves forming protective layers or masks which selectively shield underlying layers from etching. Masks are generally classified as soft masks or hard masks. A soft mask is manufactured by coating a thin layer of photoresist on a substrate. This photoresist is then exposed to a light source through a mask or reticle which defines a pattern in the photoresist. Depending on whether a positive or negative photoresist is used, the exposed portions of the photoresist are made either soluble or insoluble, respectively, in a developer. As a result, a patterned photoresist layer remains over the underlying layer after the photoresist is developed. Those portions of the underlying layer which are not covered by photoresist may then be etched using suitable etch techniques and chemistries. The pattern in the photoresist is thus replicated in the underlying layer.
Hard masks are manufactured by coating a thin layer of material on the substrate by means of deposition, sputtering or chemical vapor deposition. Materials such as sodalime or borosilicate can be used in forming the hard mask. Once deposited, the thin layer of hard mask material is then patterned using a soft mask as detailed above. The patterned hard mask then acts as a physical barrier to any subsequent etching of underlying layers covered by the hard mask.
A key limitation encountered in the above processes is lithographic rounding. Lithographic rounding occurs as a result of radiation diffraction around the edges and corners in the mask through which the photoresist is exposed. Additional lithographic rounding may be caused by the rounding of edges on the reticle itself. As illustrated in
FIG. 2
, due to lithographic rounding, even when using a reticle
102
containing sharply defined edges, the resulting pattern
104
, exposed onto the surface of the photoresist
98
, is rounded. As illustrated in
FIG. 3
, when the underlying surface
148
is etched using this patterned photoresist
98
, the rounding effect is replicated in the patterned polysilicon
148
. The lithographic rounding effect reduces the volume of the resulting capacitor cell
106
and, therefore, the capacitance is also reduced.
Petti et al., U.S. Pat. No. 5,523,258, refers to a method for using separate masks to pattern a layer of material formed over a semiconductor substrate in the fabrication of a transistor. Petti et al., however, does not teach or suggest a method for reducing the effects of lithographic rounding in the formation of openings or cavities. Rather, Petti et al. refers to patterning gate transistor material in a first direction with a single mask and then “cutting” the gate transistor material with a second mask orthogonal to the first.
As memory cell density continues to increase, efficient use of space becomes ever more important. Thus, what is needed is a process which reduces or avoids lithographic rounding effects in the fabrication of capacitors and other structures which require the formation of cavities.
SUMMARY OF THE INVENTION
The invention provides methods for patterning structures while minimizing lithographic rounding effects. The invention also provides for an enhanced capacitor shape and a method for patterning a capacitor cell which maximizes the volume of the resulting cell.
In accordance with the invention, openings are formed by patterning a s
Dickstein , Shapiro, Morin & Oshinsky, LLP
Hoang Quoc
Micro)n Technology, Inc.
Nelms David
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