Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2000-04-04
2001-11-27
Niebling, John F. (Department: 2812)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C438S106000, C438S113000, C438S612000
Reexamination Certificate
active
06323639
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to semiconductor devices, and more particularly to a structure for and a method of supplying power to the dies on a wafer during wafer testing.
As the complexity of semiconductor devices increases, the amount of time required to properly test these devices also increases. For example, with advancing technology, memory devices increase in density and complexity, and the time to properly test all memory cells and the different functions of these memory devices increases significantly. Given the high volume production of some memory devices and other semiconductor devices, the increase in test time and the corresponding testing cost can significantly increase the cost of the product.
Conventional testing of semiconductor devices includes a number of steps which can broadly be grouped into two: (i) wafer sort, for identifying defective dies at wafer level, and (ii) final test, for identifying defective packaged devices. While at final test multiple packaged devices, e.g., 8, 16, or 64, can be tested simultaneously, at wafer sort, the dies are tested sequentially. Thus, wafer sort time is significantly longer than final test time.
Conventionally, each die on a wafer is tested by placing a probe card connected to a test equipment on the contact pads of the die. The probe card supplies the proper power supply levels and control signals to the contact pads on the die. The electrical contact between the probe card and the die contact pads is maintained until the testing of the die is completed. The probe card is then moved to the next die, and the same steps are repeated. Because the number of dies on a wafer is increasing rapidly due to the increasing wafer size and the decreasing processing feature sizes, this method of sequential testing of the dies on a wafer can significantly increase the wafer sort time and cost. Thus, reducing the wafer sort time is desirable.
SUMMARY OF THE INVENTION
In accordance with the present invention, wafer testing time is significantly reduced by initiating built-in self test (BIST) operation in each of the dies of the wafer in such way that the BIST operation in a number of the dies overlap.
In one embodiment, a semiconductor wafer has a plurality of dies separated by scribe line areas. Each die has a circuit, a first contact pad configured to receive a power supply voltage, and a second contact pad configured to receive a reference voltage. The first and second pads are coupled to the circuit for powering the circuit. The scribe line areas include at least a first conductive line and a second conductive line respectively connected to the first pad and the second pad of each of the dies.
In another embodiment, each die further includes a third contact pad configured to receive a control signal to initiate a built-in self test (BIST) operation. A probe card has at least three probe pins configured to provide the power supply voltage to the first pad, the reference voltage to the second pad, and the control signal to the third pad upon bringing the probe pins into electrical contact with the respective pads.
In another embodiment, the probe pins of the probe card are brought into electrical contact with corresponding pads of a first die to initiate a BIST operation in the first die, and after initiation but before completion of the BIST operation the probe pins are removed from the first die and brought into electrical contact with a second die to initiate a BIST operation in the second die.
In another embodiment, the first conductive line has a capacitance capable of storing and supplying sufficient charge to power the first die during the portion of the BIST operation when the probe pins are removed from the first die.
In another embodiment, the circuit includes a switch coupled between the first pad and an internal power bus connected to power terminals of circuit elements in the circuit, wherein the switch is closed only during BIST operation so that power is provided to the circuit only during BIST operation.
In accordance with another embodiment of the present invention, a method for testing a plurality of dies of a wafer includes the steps of: placing the wafer in a tester for testing the plurality of dies, initiating a built-in self test (BIST) operation in a first die; and initiating a BIST operation in a second die so that the BIST operation in the first die and the BIST operation in the second die overlap.
In another embodiment, each of the plurality of dies has a circuit, and the method further includes the steps of: upon initiating the BIST operation, supplying power to the circuit, performing designed-in test operations, storing in a register data reflecting the results of the designed-in test operations, and removing power to the circuit.
In another embodiment, the method further includes the step of: upon completion of the BIST operation for all the plurality of dies, evaluating the data stored in the register of each die to determine the action to be taken with respect to each die.
The following detailed description and the accompanying drawing provide a better understanding of the nature and advantages of the present invention.
REFERENCES:
patent: 5404099 (1995-04-01), Sahara
patent: 5818748 (1998-10-01), Bertin
patent: 5918107 (1999-06-01), Fogal
patent: 6107119 (2000-08-01), Farnworth
Azalea Microelectronics Corporation
Niebling John F.
Stevenson André
Townsend and Townsend / and Crew LLP
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