Bounds checker

Details Bounds checker Bounds checker

1984-11-29

1988-07-26

Harkcom, Gary V.

Communications: electrical

Digital comparator systems

G06F 702

Patent

active

047603747

ABSTRACT:
A bounds checker consisting of a pair of comparators that each compare a 16-bit number with a lower and an upper limit stored in registers. The device is preferably constructed as a single integrated circuit chip employing emitter coupled logic (ECL) circuitry and can be made externally compatible with either transistor transistor logic (TTL) circuitry or ECL circuitry. The device can be cascaded to operate on extended-precision numbers and has a pin which can be used to select comparison of numbers either as signed two's complement numbers or as unsigned numbers. No added gate delay is imposed by the device's ability to operate either type of number.

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PAL "Programmable Array Logic Handbook", Monolithic Memories, pp. 5-60-5-66, 1977.
Hanna, "Associative Comparator", IBM Tech. Discl. Bull., vol. 25, No. 4, Sep. 1982, pp. 1871-1873.

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