Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
1999-05-03
2001-02-27
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C438S076000, C438S146000, C438S299000, C438S301000, C438S303000, C438S305000
Reexamination Certificate
active
06194748
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to an integrated circuit with transistors having suppressed gate-edge fringing effects and a method of making such transistors.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include gate stacks or structures disposed between drain and source regions. The gate structure typically includes a conductive layer that has a rectangular cross-section and a dielectric or gate oxide layer. The conductive layer is disposed over the dielectric layer. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the dielectric layer of the gate stack to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects, which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
As transistors disposed on integrated circuits (ICs) become smaller (e.g., transistors with gate lengths approaching 50 nm), transistors become more susceptible to gate-edge fringing field effects. A fringing electrical field exists near the edges of the gate stack of transistors, such as, MOSFETS. The fringing electrical field has negative effects on transistor performance. For example, the fringing field can produce a fringing overlap capacitance that is non-zero even when an overlap does not exist between the gate and the source/drain region (i.e., the gate stack and the source/drain extensions).
Generally, conventional gate dielectric materials, such as, silicon dioxide, are less applicable as transistor size is decreased. For example, gate dielectrics consisting of silicon dioxide can be subject to high leakage current caused by “direct tunneling effect.” As channel lengths approach 50 nm or less, high dielectric constant (k) dielectric materials must replace medium to low-k materials (e.g., k<8.0) as the gate dielectric layer. Silicon dioxide has a k value of approximately 3.9.
For advanced ULSI MOS transistors, high dielectric constant (k) material, such as, titanium dioxide (TiO
2
), or tantalum pentaoxide (Ta
2
O
5
), can be used as a gate insulator or a dielectric layer to suppress tunneling leakage current. In MOSFETs with high-k (k>25) gate dielectric materials, the fringing field effect near the gate stack is more significant than conventional MOSFETs, which utilize a medium or low-k dielectric material, such as, silicon dioxide. Accordingly, transistors with high-k dielectric materials are more susceptible to gate-edge fringing field effects. In small transistors, the contribution of the fringing capacitance to the total overlap capacitance can be extremely significant (e.g., more than 50 percent). The gate-edge fringing field effect can even adversely affect the ability of the gate conductor to couple to the channel and to the source/drain extensions. The gate-edge fringing field effect can also degrade the control of charges in the channel by the gate stack, thereby degrading subthreshold characteristics of the transistor.
Thus, there is a need for a MOSFET transistor that is less susceptible to gate-edge fringing field effects. Further still, there is a need for a MOSFET that includes a high-k gate dielectric material. Further still, there is a need for an efficient method of manufacturing a MOSFET that has suppressed gate-edge fringing field effects.
SUMMARY OF THE INVENTION
The present invention relates to a method of manufacturing an integrated circuit. The method includes providing a gate structure between a source region and a drain region in a semiconductor substrate. The gate structure includes a plurality of sacrificial dielectric spacers. The method also includes removing the sacrificial dielectric spacers, providing a plurality of low-k dielectric spacers, and providing an insulative layer over the gate structure.
The present invention further relates to a method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors. The method includes steps of forming at least part of a gate structure on a top surface of a semiconductor substrate and between a source and a drain. The gate structure includes a high-k gate dielectric material and a spacer. The source and the drain are covered by a silicide layer. The method also includes steps of removing the spacer, and providing a low-k gate dielectric spacer.
The present invention is even further related to an integrated circuit. The integrated circuit includes a transistor having a gate structure on a top surface of a semiconductor substrate and disposed between a source and a drain. The gate structure has a low-k dielectric spacer and a high-k gate dielectric layer.
REFERENCES:
patent: 4683645 (1987-08-01), Naguib et al.
patent: 4745082 (1988-05-01), Kwok
patent: 4784718 (1988-11-01), Mitani et al.
patent: 5264382 (1993-11-01), Watanabe
patent: 5374575 (1994-12-01), Kim et al.
patent: 5391510 (1995-02-01), Hsu et al.
patent: 5393685 (1995-02-01), Yoo et al.
patent: 5429956 (1995-07-01), Shell et al.
patent: 5593907 (1997-01-01), Anjum et al.
patent: 5607884 (1997-03-01), Byun
patent: 5675159 (1997-10-01), Oku et al.
patent: 5716861 (1998-02-01), Moslehi
patent: 5793090 (1998-08-01), Gardner et al.
patent: 5811323 (1998-09-01), Miyasaka et al.
patent: 5825066 (1998-10-01), Buynoski
patent: 5856225 (1999-01-01), Lee et al.
patent: 5858843 (1999-01-01), Doyle et al.
patent: 6020024 (2000-02-01), Maiti et al.
patent: 6059553 (2000-05-01), Jin et al.
patent: 6087234 (2000-07-01), Wu
patent: 3-248433 (1991-03-01), None
patent: 4-123439 (1992-04-01), None
patent: 5-160396 (1993-05-01), None
“Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications”, Wei William Lee, MRS Bulletin Oct. 1997.
“Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process”, A. Chatterjee, International Electronic Devices Meeting , 1997, Washington DC, Dec. 7-10, 1997.
Advanced Micro Devices , Inc.
Chaudhuri Olik
Foley & Lardner
Louie Wai-Sing
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