Semiconductor integrated circuit device having transistor...

Details Semiconductor integrated circuit device having transistor... Semiconductor integrated circuit device having transistor...

2000-11-13

2001-12-18

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S210000, C327S218000

Reexamination Certificate

active

06331796

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and, more particularly, one having a pass-transistor logic circuit and a load circuit.
DESCRIPTION OF THE PRIOR ART
Pass-transistor logic circuit technique is one of technologies for saving consumption power of LSIs or other semiconductor integrated circuit devices. In “Top-Down Pass-Transistor Logic Design” in IEEE, J. Solid State Circuits, vol. 31, pp. 792-803, 1996, an arrangement of a single-rail logic pass-transistor is proposed.
FIG. 11
shows the circuit arrangement in the literature.
As shown in
FIG. 11
, a semiconductor integrated circuit device includes a pass-transistor logic circuit
1
and a load circuit
2
. The pass-transistor logic circuit
1
is made up of n-type MOS transistors alone. In
FIG. 11
, only the final stage n-type MOS transistor
3
connected to the load circuit
2
is shown. The pass-transistor logic circuit
1
is configured to conduct various logic operations by combining these n-type MOS transistors.
The load circuit
2
includes a CMOS inverter
4
and a feedback mechanism. The feedback mechanism includes a p-type MOS transistor
5
. The CMOS inverter
4
has a p-type MOS transistor
6
and an n-type MOS transistor
7
. The load circuit
2
is connected to another circuit not shown.
Still referring to
FIG. 11
, an output signal V
1
out of the pass-transistor logic circuit
1
enters into the CMOS inverter
4
of the load circuit
2
. The inverter
4
issues an output signal V
2
out. The output signal V
2
out is supplied to another circuit not shown and also to the gate terminal of the p-type MOS transistor
5
.
Since the pass-transistor logic circuit
1
consists only of n-type MOS transistor, when the output signal V
1
out of the pass-transistor logic circuit
1
is HIGH, a voltage lower than the source voltage VDD by the threshold voltage Vtn of the n-type MOS transistor
3
is output. That is, when the output signal V
1
out of the n-type MOS transistor
3
is HIGH, VDD−Vtn is output. VDD−Vtn is not always sufficiently high. If such an insufficiently high signal is introduced into the CMOS inverter
4
operative with the source voltage VDD, both the p-type MOS transistor
6
and the n-type MOS transistor
7
are turned ON, and cause a leak current to flow continuously. That is, there occurs the problem that a leak current continues to flow from the source voltage VDD of the CMOS inverter
4
to the ground GND via the p-type MOS transistor
6
and the n-type MOS transistor
7
. Continuous flow of the leak current results in increasing the consumption power.
To prevent the leak current, the semiconductor integrated circuit device of
FIG. 11
uses a feedback mechanism having the p-type MOS transistor. More specifically, the output signal V
2
out of the CMOS inverter
4
is input to the gate terminal of the p-type MOS transistor
5
. When the input to the CMOS inverter
4
is HIGH, the output signal V
2
out is LOW. As a result, the p-type MOS transistor
5
turns ON, and the source voltage VDD of the p-type MOS transistor
5
is supplied to the input of the CMOS inverter
4
. In this manner,it is ensured that a HIGH signal of a sufficient voltage be supplied to the input of the CMOS inverter
4
by inverting and feeding the output of the CMOS inverter
4
back to the input thereof. Since a sufficiently high signal is supplied to the p-type MOS transistor
6
of the CMOS inverter
4
, the p-type MOS transistor
6
gets into a sufficient off state, and the leak current stops.
The problem of insufficiently high signals cannot occur when the output signal of the pass-transistor logic circuit
1
V
1
out is LOW because, when the input to the n-type MOS transistor
3
is 0 V, the n-type MOS transistor
3
outputs 0 V. That is, output signal V
1
out of the pass-transistor logic circuit
1
becomes a sufficiently low signal. Due to the sufficiently low signal output from the pass-transistor logic circuit
1
, the n-type MOS transistor
7
of the CMOS inverter
4
gets in a sufficiently off state, and the p-type MOS transistor
6
turns on. As a result, although the CMOS inverter
4
outputs a HIGH signal as the output signal V
2
out, no leak current flows.
Therefore, by connecting the output of the CMOS inverter
4
to the gate terminal of the p-type MOS transistor
5
for the feedback purpose, the input to the CMOS inverter
4
is ensured to be sufficiently low or sufficiently high, and a continuous leak current can be prevented.
FIG. 12
shows another conventional semiconductor integrated circuit device. In the semiconductor integrated circuit device shown here, a load circuit
2
′ includes two inverters
4
for the purpose of achieving high-speed operation. More specifically, by independently providing the inverter
4
forming the feedback mechanism and the inverter
4
for supplying the output signal V
2
out to another circuit, the load to the CMOS inverter
4
serving to supply the signal to another circuit is decreased to ensure high-speed operation. Also the semiconductor integrated circuit device shown in
FIG. 12
operates similarly. Therefore, the input to the CMOS inverter
4
is ensured to be sufficiently low or sufficiently high, and the continuous leak current can be prevented.
These arrangements, however, still involve problems explained below. Referring to
FIG. 11
, for example, when the output signal V
1
out from the pass-transistor logic circuit
1
changes from HIGH to LOW, there occurs a state where the input voltage to the n-type MOS transistor
3
is LOW and the p-type MOS transistor
5
for the feedback purpose is ON. In this state, a short-circuit current flows from the source voltage VDD of the p-type MOS transistor
5
to the input voltage-to the source terminal of the n-type MOS transistor
3
. That is, since the source voltage VDD of the source terminal S of the p-type MOS transistor
5
and the ground of the source terminal S is short-circuited, a large current flows.
For recovery from this state, it is necessary that the force for changing the input to the CMOS inverter
4
in the pass-transistor logic circuit
1
to LOW is greater than the force for maintaining the high state in the p-type MOS transistor
5
. That is, the n-type MOS transistor
3
must be stronger than the p-type MOS transistor
5
. Therefore, a ratio design is required for the circuit arrangement. The circuit of a ratio design, however, operates differently depending upon sizes of MOS transistors. Additionally, circuits of a ratio design require a circuit design allowing for variances in the process for fabricating MOS transistors, namely, a large design margin.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a semiconductor circuit device capable of preventing a leak current of a CMOS inverter in a load circuit without using a feedback mechanism. That is, it is the object of the invention to provide a semiconductor circuit device including a pass-transistor logic circuit and a load circuit which do not require a ratio design.
According to the invention, there is provided a semiconductor integrated circuit device comprising:
a pass-transistor logic circuit having at least one n-type MOS transistor for a logic circuit to supply a logic output signal; and
a load circuit having a CMOS inverter including a p-type MOS transistor forming the CMOS inverter and an n-type MOS transistor forming the CMOS inverter which are connected in series between a first power source and a second power source, the p-type MOS transistor forming the CMOS inverter and the n-type MOS transistor forming the CMOS inverter having gate terminals supplied with the logic output signal forming the input of said CMOS inverter, the p-type MOS transistor forming the CMOS inverter and the n-type MOS transistor forming the CMOS inverter having a common connected point from which a load output signal is output and which forms the output of the CMOS inverter, and said p-type MOS transistor forming the CMOS inverter having a threshold voltage value who

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